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78k/0 series 8-bit single-chip microcontroller basic ( i ) m pd78002 subseries m pd78002y subseries m pd78014 subseries m pd78014y subseries m pd78018f subseries m pd78018fy subseries m pd780024 subseries m pd780024y subseries m pd780034 subseries m pd780034y subseries m pd78014h subseries m pd780924 subseries m pd780964 subseries m pd780001 document no. u12704ej7v1an00 (7th edition) date published july 1998 n cp(k) 1991 application note printed in japan
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purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. fip, eeprom, and iebus are trademarks of nec corporation. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j98. 2
major revisions in this edition page description addition of following products as applicable products: m pd780024, 780024y, 780034, 780034y, 78014h, 780924, 780964 subseries, m pd78018f, 78018fy, 780001, 78011f(a), 78012f(a), 78013f(a), 78014f(a), 78015f(a), 78016f(a), 78018f(a), 78p018f(a) following register formats and tables are shown for each model. tables 3-1 and 3-2 maximum time required to switch cpu clock figures 3-1 through 3-4 format of processor clock control register figures 4-1 and 4-2 format of timer clock select register 2 figures 4-4 through 4-6 format of watchdog timer mode register figures 5-2 and 5-3 format of 16-bit timer mode control register figures 5-4 and 5-5 format of 16-bit timer output control register figures 7-2 and 7-3 format of watch timer mode control register figures 9-1 through 9-4 format of a/d converter mode register figures 9-5 and 9-6 format of a/d converter input select register addition of following register formats: figure 4-3 format of watchdog timer clock select register figure 5-9 format of capture/compare control register 0 figure 5-10 format of prescaler mode register 0 figures 5-11 and 5-14 format of port mode register 7 figures 6-2 and 6-3 format of timer clock select register 50 figures 6-4 and 6-5 format of timer clock select register 51 figures 6-6 format of timer clock select register 52 figures 6-8 format of 8-bit timer mode control register 5n figures 6-9 format of 8-bit timer mode control register 50 figures 6-10 format of 8-bit timer mode control register 51 figures 6-11 format of 8-bit timer mode control register 52 figure 9-7 format of analog input channel specification register addition of note 2 and caution 2 to figure 4-4 format of watchdog timer mode register addition of caution to figure 5-7 format of external interrupt mode register addition of table 8-2 registers of serial interface addition of caution to figures 8-6 through 8-8 format of serial operating mode register 0, and note to control of wake-up function addition of caution to figure 8-19 format of automatic transmission/reception interval specification register change of m pd6252 as maintenance part in 8.1 interface with eeprom tm ( m pd6252) addition of (5) and (6) limits when i 2 c bus mode is used to 8.1.2 communication in i 2 c bus mode addition of hsc bit to figure 9-2 format of a/d converter mode register the mark shows major revised points. p.57, 58 p.59 to p.62 p.70, p71 p73 to p.75 p.81, 82 p.83, 84 p.145, 146 p.264 to p267 p.268, 269 p.72 p.86 p.87 p.87, 133 p.125 p.126 p.127 p.128 p.129 p.130 p.131 p.269 p.73 p.85 p.155 p.161 to p.166 p.182 p.185 p.203 p.265 throughout
introduction readers this application note is intended for use by engineers who understand the functions of the 78k/0 series and wish to design application programs with the following subseries products: ? subseries m pd78002 subseries : m pd78001b, 78002b, 78001b(a), 78002b(a) m pd78002y subseries : m pd78001by, 78002by m pd78014 subseries : m pd78011b, 78012b, 78013, 78014, 78p014, 78011b(a), 78012b(a), 78013(a), 78014(a) m pd78014y subseries : m pd78011by, 78012by, 78013y, 78014y, 78p014y m pd78018f subseries : m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f, 78p018f, 78011f(a), 78012f(a), 78013f(a), 78014f(a), 78015f(a), 78016f(a), 78018f(a), 78p018f(a), 78012f(a2) m pd78018y subseries : m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy, 78018fy, 78p018fy m pd780001 m pd78014h subseries : m pd78011h, 78012h, 78013h, 78014h, 78011h(a), 78012h(a), 78013h(a), 78014h(a) m pd780024 subseries : m pd780021 note , 780022 note , 780023 note , 780024 note m pd780024y subseries : m pd780021y note , 780022y note , 780023y note , 780024y note m pd780034 subseries : m pd780031 note , 780032 note , 780033 note , 780034 note , 78f0034 note m pd780034y subseries : m pd780031y note , 780032y note , 780033y note , 780034y note , 78f0034y note m pd780924 subseries : m pd780921 note , 780922 note , 780923 note , 780924 note , 78f0924 note m pd780964 subseries : m pd780961 note , 780962 note , 780963 note , 78f0964 note note under development remarks 1. the m pd78001b(a), and 78002b(a) have higher reliability than the m pd78001b and 78002b. 2. the m pd78011b(a), 78012b(a), 78013(a) and 78014(a) have higher reli- ability than the m pd78011b, 78012b, 78013 and 78014. 3. the m pd78011f(a), 78012f(a), 78013f(a), 78014f(a), 78015f(a), 78016f(a), 78018f(a), and 78p018f(a) have higher reliability than the m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f, and 78p018f. 4. the m pd78012f(a2) has higher reliability than the m pd78012f. 5. the m pd78011h(a), 78012h(a), 78013h(a), and 78014h(a) have higher reliability than the m pd78011h, 78012h, 78013h, and 78014h. purpose this application note is to deepen your understanding of the basic functions of the 78k/ 0 series by using program examples. note that the programs and hardware configuration shown in this document are only examples and not subject to mass production.
organization this application note consists of the following contents: ? general ? software ? hardware in addition to this application note, the following application notes are also available: document number japanese english 78k/0 series u12704j this m pd78002, 78002y application note document m pd78014, 78014y basic (i) m pd78018f, 78018fy m pd780001 m pd780024, 780024y m pd780034, 780034y m pd78014h m pd780924 m pd780964 78k/0 series u10121j u10121e m pd78044 application note m pd78044h basic (ii) m pd780208 m pd780228 78k/0 series u10182j u10182e m pd78054, 78054y application note m pd78064, 78064y basic (iii) m pd78078, 78078y m pd78083 m pd78098 m pd780018ay m pd780058, 780058y m pd780308, 780308y m pd78058f, 78058fy m pd78064b m pd78070a, 78070ay m pd78075b, 78075by m pd78098b 78k/0 series iea-718 iea-1289 all subseries in 78k/0 application note series floating-point except m pd78002 and operation program 78002y subseries m pd78014 series iea-744 iea-1301 m pd78014 application note only m pd78014 and electronic pocketbook 78p014 caution the application examples and program lists shown in this application note assume that the main system clock operates at 8.38 mhz, not at 10.0 mhz. document name targeted subseries contents explains basic functions of products in 78k/0 series by using program examples explains floating-point operation programs of products in 78k/0 series explains how to organize electronic pocketbook by using m pd78014 subseries
how to read this manual although this application note explains the functions of the 78k/0 series products, the functions of some products in each subseries differ from those of the others. subseries m pd78002 m pd78014 m pd78018f m pd780001 m pd780024 m pd780034 m pd78014h m pd780924 chapter m pd78002y m pd78014y m pd78018fy m pd780024y m pd780034y m pd780964 chapter 1 general chapter 2 basics of software chapter 3 applications of system clock selection chapter 4 applications of watchdog timer chapter 5 applications of 16-bit timer/event counter chapter 6 applications of 8-bit timer/event counter chapter 7 applications of watch timer chapter 8 applications of serial interface chapter 9 applications of a/d converter chapter 10 applications of key input the (a)-model and standard models differ only in quality grade. the m pd78012f(a2) differs from standard models and (a)-models in terms of operating temperature range, dc characteristics, and ac characteristics. for details, refer to the individual data sheet. in this document, read (a)-models and (a2)-model as follows: m pd78001b ? m pd78001b(a) m pd78002b ? m pd78002b(a) m pd78011b ? m pd78011b(a) m pd78012b ? m pd78012b(a) m pd78013 ? m pd78013(a) m pd78014 ? m pd78014(a) m pd78011f ? m pd78011f(a) m pd78012f ? m pd78012f(a) m pd78013f ? m pd78013f(a) m pd78014f ? m pd78014f(a) m pd78015f ? m pd78015f(a) m pd78016f ? m pd78016f(a) m pd78018f ? m pd78018f(a) m pd78p018f ? m pd78p018f(a) m pd78011h ? m pd78011h(a) m pd78012h ? m pd78012h(a) m pd78013h ? m pd78013h(a) m pd78014h ? m pd78014h(a) m pd78012f ? m pd78012f(a2) C C C C C CC C C CC C C
legend data significance : left: higher digit, right: lower digit low active : (top bar over pin or signal name) note : description of note in the text caution : important information remark : supplement numeric representation : binary ... or b decimal ... hexadecimal ... h quality grade ? standard m pd78001b, 78002b m pd78001by, 78002by m pd78011b, 78012b, 78013, 78014, 78p014 m pd78011by, 78012by, 78013y, 78014y, 78p014y m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78p018f m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy, 78p018fy m pd78001 m pd780021, 780022, 780023, 780024 m pd780021y, 780022y, 780023y, 780024y m pd780031, 780032, 780033, 780034, 78f0034 m pd780031y, 780032y, 780033y, 780034y, 78f0034y m pd78011h, 78012h, 78013h, 78014h m pd780921, 780922, 780923, 780924, 78f0924 m pd780961, 780962, 780963, 780964, 78f0964 ? special m pd78001b(a), 78002b(a) m pd78011b(a), 78012b(a), 78013(a), 78014(a) m pd78011f(a), 78012f(a), 78013f(a), 78014f(a), 78015f(a), 78016f(a), 78018f(a), 78p018f(a), 78012f(a2) m pd78011h(a), 78012h(a), 78013h(a), 78014h(a) please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. application field ? consumer appliances
related documents some of the related documents listed below are preliminary versions but not so specified here. ? common related documents document number japanese english 78k/0 series application note - basic (i) u12704j this document 78k/0 series users manual - instruction u12326j u12326e 78k/0 series instruction set u10904j C 78k/0 series instruction table u10903j C ? documents dedicated to product ? m pd78002, 78002y subseries document number japanese english m pd78002, 78002y series users manual u10039j u10039e m pd78001b, 78002b data sheet u10674j u10674e m pd78001b(a), 78002b(a) data sheet ic-9078 ic-3599 m pd78001by, 78002by data sheet ic-8571 ic-3173 m pd78002, 78002y series special function register table iem-5547 C ? m pd78014, 78014y subseries document number japanese english m pd78014, 78014y series users manual u10085j u10085e m pd78011b, 78012b, 78013, 78014 data sheet ic-8201 ic-3179 m pd78011b(a), 78012b(a), 78013(a), 78014(a) data sheet ic-8874 ic-3411 m pd78011by, 78012by, 78013y, 78014y data sheet ic-8573 ic-3405 m pd78p014 data sheet ic-8111 ic-3098 m pd78p014y data sheet ic-8572 ic-3180 m pd78014, 78014y series special function register table iem-5527 C document name document name document name
? m pd78018f, 78018fy subseries document number japanese english m pd78018f, 78018fy subseries users manual u10659j u10659e m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f data sheet u10280j u10280e m pd78011f(a), 78012f(a), 78013f(a), 78014f(a), 78015f(a), 78016f(a) u11921j u11921e 78018f(a) data sheet m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy u10281j u10281e data sheet m pd78p018f data sheet u10955j u10955e m pd78p018f(a) data sheet u12132j u12132e m pd78p018fy data sheet u10989j u10989e m pd78018f subseries special function register table iem-5594 C m pd78018fy subseries special function register table u10287j C ? m pd780001 subseries document number japanese english m pd780001 users manual u10885j u10885e m pd780001 data sheet u10324j u10324e ? m pd780024, 780024y, 780034, 780034y subseries document number japanese english m pd780021, 780022, 780023, 780024 preliminary product information u12299j u12299e m pd780031, 780032, 780033, 780034 preliminary product information u12300j u12300e m pd78f0034 preliminary product information u11993j u11993e m pd780021y, 780022y, 780023y, 780024y preliminary product information u12165j u12165e m pd780031y, 780032y, 780033y, 780034y preliminary product information u12166j u12166e m pd78f0034y preliminary product information u11994j u11994e m pd780024, 780034, 780024y, 780034y subseries users manual u12022j u12022e ? m pd78014h subseries document number japanese english m pd78014h subseries users manual u12220j u12220e m pd78011h, 78012h, 78013h, 78014h data sheet u11898j u11898e m pd78011h(a), 78012h(a), 78013h(a), 78014h(a) data sheet u12174j u12174e document name document name document name document name
? m pd780924, 780964 subseries document number japanese english m pd780921, 780922, 780923, 780924 preliminary product information u11804j u11804e m pd78f0924 preliminary product information u11930j u11930e m pd780961, 780962, 780963, 780964 preliminary product information u11879j u11879e m pd78f0964 preliminary product information u11956j u11956e m pd780924, 780964 subseries users manual u12071j u12071e m pd780924, 780964 subseries special funciton register table u12230j C the contents of the above related documents are subject to change without notice. be sure to use the latest edition when you design your system. document name
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C i C contents chapter 1 general ................................................................................................................. 1 1.1 product development of 78k/0 series ....................................................................... 1 1.2 features of 78k/0 series .............................................................................................. 3 chapter 2 basics of software ......................................................................................... 37 2.1 data transfer .................................................................................................................. 37 2.2 data comparison ........................................................................................................... 38 2.3 decimal addition ........................................................................................................... 39 2.4 decimal subtraction ...................................................................................................... 46 2.5 binary-to-decimal conversion ..................................................................................... 48 2.6 bit manipulation instruction ......................................................................................... 49 2.7 binary multiplication (16 bits 16 bits) ..................................................................... 50 2.8 binary division (32 bits ? 16 bits) ............................................................................... 53 chapter 3 application of system clock selection ............................................... 57 3.1 changing pcc immediately after reset ................................................................... 63 3.2 selecting power on/off .............................................................................................. 65 chapter 4 applications of watchdog timer ............................................................. 69 4.1 setting watchdog timer mode .................................................................................... 76 4.2 setting interval timer mode ......................................................................................... 77 chapter 5 applications of 16-bit timer/event counter ........................................ 79 5.1 setting of interval timer ............................................................................................... 88 5.2 pwm output .................................................................................................................... 89 5.3 remote controller signal reception .......................................................................... 91 5.3.1 remote controller signal reception by counter clearing ................................................ 93 5.3.2 remote controller signal reception by pwm output and free running mode ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries only) ............................... 107 chapter 6 applications of 8-bit timer/event counter .......................................... 123 6.1 setting of interval timer ............................................................................................... 134 6.1.1 setting of 8-bit timers ...................................................................................................... 135 6.1.2 setting of 16-bit timer ...................................................................................................... 136 6.2 musical scale generation ............................................................................................. 137 chapter 7 applications of watch timer ...................................................................... 143 7.1 watch and led display program ................................................................................ 147 chapter 8 applications of serial interface ............................................................ 155 8.1 interface with eeprom tm ( m pd6252) ......................................................................... 185 8.1.1 communication in 2-wire serial i/o mode ...................................................................... 187 8.1.2 communication in i 2 c bus mode .................................................................................... 195 8.2 interface with osd lsi ( m pd6451a) ............................................................................ 208
C ii C 8.3 interface in sbi mode .................................................................................................... 213 8.3.1 application as master cpu ............................................................................................. 215 8.3.2 application as slave cpu ................................................................................................ 223 8.4 interface in 3-wire serial i/o mode ............................................................................. 226 8.4.1 application as master cpu ............................................................................................. 227 8.4.2 application as slave cpu ................................................................................................ 230 8.5 half-duplex start-stop synchronization communication ....................................... 233 8.5.1 half-duplex start-stop synchronization communication in 3-wire serial i/o mode ....... 233 8.5.2 half-duplex start-stop synchronization communication in sbi mode ............................ 247 chapter 9 applications of a/d converter .................................................................. 263 9.1 level meter ..................................................................................................................... 270 9.2 thermometer .................................................................................................................. 279 9.3 analog key input ........................................................................................................... 289 9.4 4-channel input a/d conversion ................................................................................. 295 chapter 10 applications of key input ............................................................................ 299 appendix a description of spd chart ............................................................................. 305 appendix b revision history ............................................................................................... 313
C iii C list of figures (1/4) fig. no. title page 1-1. block diagram of m pd78002 subseries ....................................................................................... 4 1-2. block diagram of m pd78002y subseries .................................................................................. 6 1-3. block diagram of m pd78014 subseries .................................................................................... 8 1-4. block diagram of m pd78014y subseries .................................................................................. 11 1-5. block diagram of m pd78018f subseries .................................................................................. 14 1-6. block diagram of m pd78018fy subseries ............................................................................... 17 1-7. block diagram of m pd780001 .................................................................................................... 20 1-8. block diagram of m pd780024 subseries .................................................................................. 22 1-9. block diagram of m pd780024y subseries ................................................................................ 24 1-10. block diagram of m pd780034 subseries .................................................................................. 26 1-11. block diagram of m pd780034y subseries ................................................................................ 28 1-12. block diagram of m pd78014h subseries ................................................................................. 30 1-13. block diagram of m pd780924 subseries .................................................................................. 32 1-14. block diagram of m pd780924 subseries .................................................................................. 34 2-1. data exchange ............................................................................................................................ 37 2-2. data comparison ........................................................................................................................ 38 2-3. decimal addition ......................................................................................................................... 39 2-4. decimal subtraction .................................................................................................................... 46 2-5. binary-to-decimal conversion .................................................................................................... 48 2-6. bit operation ............................................................................................................................... 49 2-7. binary multiplication .................................................................................................................... 50 2-8. binary division ............................................................................................................................ 53 3-1. format of processor clock control register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries) ...................................................................................... 59 3-2. format of processor clock control register ( m pd780001) ..................................................... 60 3-3. format of processor clock control register ( m pd780024, 780024y, 780034, 780034y subseries) ............................................................................................................................... ..... 61 3-4. format of processor clock control register ( m pd780924, 780964 subseries) ...................... 62 3-5. example of selecting cpu clock after reset ......................................................................... 63 3-6. example of system clock changing circuit .............................................................................. 65 3-7. example of changing system clock on power on/off ......................................................... 66 4-1. format of timer clock select register 2 ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries) ..................................................................................................... 70 4-2. format of timer clock select register 2 ( m pd780001) ........................................................... 71 4-3. format of watchdog timer clock select register ( m pd780024, 780024y, 780034, 780034y, 780924, 780964 subseries) ....................................................................................... 72 4-4. format of watchdog timer mode register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) ............................................................................... 73 4-5. format of watchdog timer mode register ( m pd780024, 780024y, 780034, 780034y subseries) ............................................................................................................................... ..... 74
C iv C list of figures (2/4) fig. no. title page 4-6. format of watchdog timer mode register ( m pd780924, 780964 subseries) ....................... 75 4-7. count timing of watchdog timer .............................................................................................. 77 5-1. format of timer clock select register 0 ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) ...................................................................................................................... 80 5-2. format of 16-bit timer mode control register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) ...................................................................................................................... 81 5-3. format of 16-bit timer mode control register ( m pd780024, 780024y, 780034, 780034y subseries) ............................................................................................................................... ..... 82 5-4. format of 16-bit timer output control register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) ...................................................................................................................... 83 5-5. format of 16-bit timer output control register ( m pd780024, 780024y, 780034, 780034y subseries) .................................................................................................................... 84 5-6. format of port mode register 3 ( m pd78014, 78014y, 78018, 78018fy, 78014h subseries) ............................................................................................................................... ..... 85 5-7. format of external interrupt mode register ( m pd78014, 78014y, 78018, 78018fy, 78014h subseries) ...................................................................................................................... 85 5-8. format of sampling clock select register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) ...................................................................................................................... 86 5-9. format of capture/compare control register 0 ( m pd780024, 780024y, 780034, 780034y subseries) ............................................................................................................................... ..... 86 5-10. format of prescaler mode register 0 ( m pd780024, 780024y, 780034, 780034y subseries) ............................................................................................................................... ..... 87 5-11. format of port mode register 7 ( m pd780024, 780024y, 780034, 780034y subseries) ...... 87 5-12. example of remote controller signal receiver circuit ............................................................ 91 5-13. remote controller signal transmitter ic output signal ........................................................... 92 5-14. output signal of receiver preamplifier ..................................................................................... 92 5-15. sampling of remote controller signal ....................................................................................... 93 6-1. format of timer clock select register 1 ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries m pd780001) ................................................................................ 124 6-2. format of timer cock select register 50 ( m pd780024, 780024y, 780034, 780034y subseries) ............................................................................................................................... ..... 125 6-3. format of timer cock select register 50 ( m pd780924, 780964 subseries) .......................... 125 6-4. format of timer cock select register 51 ( m pd780024, 780024y, 780034, 780034y subseries) ............................................................................................................................... ..... 126 6-5. format of timer cock select register 51 ( m pd780924, 780964 subseries) .......................... 126 6-6. format of timer cock select register 52 ( m pd780924, 780964 subseries) .......................... 127 6-7. format of 8-bit timer mode control register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) ................................................................ 127 6-8. format of 8-bit timer mode control register 5n ( m pd780024, 780024y, 780034, 780034y subseries) .................................................................................................................... 128 6-9. format of 8-bit timer mode control register 50 ( m pd780924, 780964 subseries) .............. 129
C v C list of figures (3/4) fig. no. title page 6-10. format of 8-bit timer mode control register 51 ( m pd780924, 780964 subseries) .............. 130 6-11. format of 8-bit timer mode control register 52 ( m pd780924, 780964 subseries) .............. 131 6-12. format of 8-bit timer output control register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) ................................................................ 132 6-13. format of port mode register 3 ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) ................................................................................................ 133 6-14. format of port mode register 7 ( m pd780024, 780024y, 780034, 780034y subseries) ........ 133 6-15. count timing of 8-bit timers ....................................................................................................... 134 6-16. musical scale generation circuit ............................................................................................... 137 6-17. timer output and interval ........................................................................................................... 137 7-1. format of timer clock select register 2 ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries) ........................................................................................................ 144 7-2. format of watch timer mode control register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries) .......................................................................................... 145 7-3. format of watch timer mode control register ( m pd780024, 780024y, 780034, 780034y subseries) ............................................................................................................................... ......... 146 7-4. concept of watch data .................................................................................................................. 147 7-5. led display timing ........................................................................................................................ 148 7-6. circuit example of watch timer .................................................................................................... 148 8-1. format of timer clock select register 3 ( m pd78002 subseries) ................................................ 156 8-2. format of timer clock select register 3 ( m pd78002y subseries) ............................................. 157 8-3. format of timer clock select register 3 ( m pd78014, 78018f, 78014h subseries) .................. 158 8-4. format of timer clock select register 3 ( m pd78014y, 78018fy subseries) ............................ 159 8-5. format of timer clock select register 3 ( m pd780001) ............................................................... 160 8-6. format of serial operating mode register 0 ( m pd78002, 78014, 78018f, 78014h subseries) ............................................................................................................................... ......... 161 8-7. format of serial operating mode register 0 ( m pd78002y, 78014y subseries) ........................ 163 8-8. format of serial operating mode register 0 ( m pd78018fy subseries) ..................................... 165 8-9. format of serial operating mode register 1 ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries only) .................................................................................................................. 167 8-10. format of serial operating mode register 1 ( m pd780001) ......................................................... 168 8-11. format of interrupt timing specification register ( m pd78002, 78014 subseries) ..................... 169 8-12. format of interrupt timing specification register ( m pd78002y, 78014y subseries) ................. 170 8-13. format of interrupt timing specification register ( m pd78018f, 78014h subseries) ................. 172 8-14. format of interrupt timing specification register ( m pd78018fy subseries) ............................. 173 8-15. format of serial bus interface control register ( m pd78002, 78014, 78018f, 78014h subseries) ............................................................................................................................... ......... 175 8-16. format of serial bus interface control register ( m pd78002y, 78014y subseries) ................... 177 8-17. format of serial bus interface control register ( m pd78018fy subseries) ................................ 179 8-18. format of automatic data transmit/receive control register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries only) ................................................................................................ 181
C vi C list of figures (4/4) fig. no. title page 8-19. format of automatic data transmit/receive interval specification register ( m pd78018f, 78018fy, 78014h subseries only) ................................................................................................ 182 8-20. pin configuration of m pd6252 ....................................................................................................... 185 8-21. example of connection of m pd6252 ............................................................................................. 187 8-22. communication format of m pd6252 ............................................................................................. 188 8-23. example of connection between m pd6252 and i 2 c bus mode ................................................... 195 8-24. m pd6252 operation timing ............................................................................................................ 196 8-25. example of connecting m pd6451a ............................................................................................... 208 8-26. communication format of m pd6451a ........................................................................................... 208 8-27. example of connection in sbi mode ............................................................................................. 213 8-28. communication format in sbi mode ............................................................................................. 214 8-29. ack signal in case of time out .................................................................................................... 215 8-30. testing bus line ............................................................................................................................. 21 5 8-31. example of connection in 3-wire serial i/o mode ....................................................................... 226 8-32. communication format in 3-wire serial i/o mode ....................................................................... 226 8-33. output of busy signal .................................................................................................................... 230 8-34. system configuration (in 3-wire serial i/o mode) ......................................................................... 233 8-35. transmission format in 3-wire serial i/o mode .......................................................................... 234 8-36. reception format in 3-wire serial i/o mode ................................................................................ 235 8-37. system configuration (sbi mode) ................................................................................................. 247 8-38. transmission format in sbi mode ................................................................................................ 248 8-39. reception format in sbi mode ...................................................................................................... 249 9-1. format of a/d converter mode register ( m pd78014, 78014y subseries, m pd780001) .......... 264 9-2. format of a/d converter mode register ( m pd78018f, 78018fy, 78014h subseries) .............. 265 9-3. format of a/d converter mode register ( m pd780024, 780024y subseries) ............................. 266 9-4. format of a/d converter mode register ( m pd780924 subseries) .............................................. 267 9-5. format of a/d converter input select register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) .......................................................................................................................... 268 9-6. format of a/d converter input select register ( m pd780001) ..................................................... 269 9-7. format of analog input channel specification register ( m pd780024, 780024y, 780924 subseries) ............................................................................................................................... ......... 269 9-8. example of level meter circuit ...................................................................................................... 270 9-9. a/d conversion result and display .............................................................................................. 270 9-10. concept of peak hold .................................................................................................................... 271 9-11. circuit example of thermometer ................................................................................................... 279 9-12. temperature vs. output characteristic ......................................................................................... 280 9-13. example of analog key input circuit ............................................................................................. 290 9-14. timing chart in 4-channel scan mode ......................................................................................... 295 10-1. key matrix circuit ........................................................................................................................... 299
C vii C list of tables table. no. title page 1-1. functional outline of m pd78002 subseries .............................................................................. 5 1-2. functional outline of m pd78002y subseries ............................................................................ 7 1-3. functional outline of m pd78014 subseries .............................................................................. 9 1-4. functional outline of m pd78014y subseries ............................................................................ 12 1-5. functional outline of m pd78018f subseries ............................................................................ 15 1-6. functional outline of m pd78018fy subseries .......................................................................... 18 1-7. functional outline of m pd780001 .............................................................................................. 21 1-8. functional outline of m pd780024 subseries ............................................................................ 23 1-9. functional outline of m pd780024y subseries .......................................................................... 25 1-10. functional outline of m pd780034 subseries ............................................................................ 27 1-11. functional outline of m pd780034y subseries .......................................................................... 29 1-12. functional outline of m pd78014h subseries ............................................................................ 31 1-13. functional outline of m pd780924 subseries ............................................................................ 33 1-14. functional outline of m pd780964 subseries ............................................................................ 35 3-1. maximum time required for changing cpu clock ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 780024, 780024y, 780034, 780034y, 78014h subseries) ....................... 57 3-2. maximum time required for changing cpu clock ( m pd780924, 780964 subseries, m pd780001) ............................................................................................................................... .58 3-3. relation between cpu clock and minimum instruction execution time ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) ...................... 60 3-4. relation between cpu clock and minimum instruction execution time (other than m pd780024, 780024y, 780034, 780034y, 780924, 780964 subseries) .................................. 62 5-1. valid time of input signal .......................................................................................................... 93 5-2. valid time of input signal .......................................................................................................... 107 6-1. musical scale and frequency .................................................................................................... 138 8-1. serial interface channel of each subseries ............................................................................. 155 8-2. registers of serial interface ....................................................................................................... 155 8-3. pin function of m pd6252 ........................................................................................................... 186 8-4. m pd6252 commands .................................................................................................................. 187 8-5. signals in sbi mode ................................................................................................................... 214 9-1. a/d conversion value and temperature ................................................................................... 281 9-2. input voltage and key code ...................................................................................................... 289 9-3. resistances of r1 through r5 ................................................................................................... 290 a-1. comparison between spd symbols and flowchart symbol .................................................... 305
C viii C [memo]
1 chapter 1 general chapter 1 general 1.1 product development of 78k/0 series the following shows the products organized according to usage. the names in the parallelograms are subseries names. note under planning 64-pin 64-pin 64-pin 64-pin 80-pin 80-pin emi-noise reduced version of the pd78054 uart and d/a converter were enhanced to the pd78014 and i/o was enhanced pd78054 pd78054y pd78058f pd78058fy pd780034 pd780024 pd780964 pd780924 pd780034y pd780024y m m m m m m m m m m 64-pin a/d converter of the pd780024 was enhanced serial i/o of the pd78018f was added and emi-noise was reduced. on-chip inverter control circuit and uart. emi-noise was reduced. m m m m a/d converter of the pd780924 was enhanced m pd78044f pd78044h 80-pin 80-pin pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y pd78098 80-pin pd78p0914 64-pin 78k/0 series an n-ch open drain i/o was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 lcd drive the sio of the pd78064 was enhanced, and rom, ram capacity increased emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart iebus tm supported an iebus controller was added to the pd78054 lv on-chip pwm output, lv digital code decoder, and hsync counter m m m m m m m m m m m m m m m m pd78083 pd78002 pd78002y pd780001 pd78014 pd78014y pd78018f pd78018fy low-voltage (1.8 v) operation version of the pd78014, with larger selection of rom and ram capacities an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) m m m m m m m m 42/44-pin 64-pin 64-pin 64-pin 64-pin pd78014h m emi-noise reduced version of the pd78018f m m pd780058 pd780058y note m m 80-pin serial i/o of the pd78054 was enhanced and emi-noise was reduced. 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. a timer was added to the pd78054 and external interface was enhanced rom-less version of the pd78078 pd78070a pd78070ay m pd78078 pd78078y pd780018ay m m m m m 100-pin serial i/o of the pd78078y was enhanced and the function is limited. m m 100-pin control pd78075b pd78075by m m emi-noise reduced version of the pd78078 m inverter control pd780228 100-pin the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 m m m pd780208 100-pin fip tm drive the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 m m pd780208 m pd78098b emi-noise reduced version of the pd78098 m 80-pin m meter control on-chip automobile meter driving controller/driver pd780973 m 80-pin
2 chapter 1 general the following lists the main functional differences between subseries products. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32k-40k 4ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 88 1.8 v m pd78078 48k-60k m pd78070a C 61 2.7 v m pd780058 24k-60k 2ch 2ch 3ch (time division uart: 1ch) 68 1.8 v m pd78058f 48k-60k 3ch (uart: 1ch) 69 2.7 v m pd78054 16k-60k 2.0 v m pd780034 8k-32k C 8ch C 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch C time division 3-wire: 1ch) m pd78014h 2ch 53 1.8 v m pd78018f 8k-60k m pd78014 8k-32k 2.7 v m pd780001 8k C C 1ch 39 C m pd78002 8k-16k 1ch C 53 m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C inverter m pd780964 8k-32k 3ch note C 1ch C 8ch C 2ch (uart: 2ch) 47 2.7 v control m pd780924 8ch C fip m pd780208 32k-60k 2ch 1ch 1ch 1ch 8ch C C 2ch 74 2.7 v C drive m pd780228 48k-60k 3ch C C 1ch 72 4.5 v m pd78044h 32k-48k 2ch 1ch 1ch 68 2.7 v m pd78044f 16k-40k 2ch lcd m pd780308 48k-60k 2ch 1ch 1ch 1ch 8ch C C 3ch (time division uart: 1ch) 57 2.0 v C drive m pd78064b 32k 2ch (uart: 1ch) m pd78064 16k-32k iebus m pd78098 40k-60k 2ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 69 2.7 v supported m pd78098b 32k-60k meter m pd780973 24k-32k 3ch 1ch 1ch 1ch 5ch C C 2ch (uart: 1ch) 56 4.5 v C control lv m pd78p0914 32k 6ch C C 1ch 8ch C C 2ch 54 4.5 v note 10-bit timer: 1 channel
3 chapter 1 general 1.2 features of 78k/0 series the 78k/0 series is a collection of 8-bit single-chip microcontrollers ideal for consumer applications. the m pd78002 and 78002y subseries are microcontrollers with many hardware peripherals such as rom, ram, i/o ports, timers, serial interface, and interrupt control functions, as well as a high-speed, high-performance cpu. the m pd78014 and 78014y subseries are models with an a/d converter and a reinforced timer and serial interface in addition to the above hardware peripherals. the m pd78018f and 78018fy subseries are models that can operate at a voltage lower than the m pd78014 and 78014y subseries. the m pd780001 is based on the m pd78002 subseries model and is provided with an a/d converter. the m pd780024 and 780024y subseries are low-emi noise versions of the m pd78018f and 78018fy subseries with a reinforced serial i/o interface. the m pd780034 and 780034y subseries are low-emi noise versions of the m pd780024 and 780024y subseries with a reinforced a/d converter. the m pd78014h subseries is a low-emi noise version of the m pd78018f subseries. the m pd780924 and 780964 subseries are provided with an inverter control circuit. the m pd780924 subseries is a low-emi noise model. the m pd780964 subseries is a version of the m pd780924 subseries with a reinforced a/ d converter. the m pd78002y, 78014y, 780024y, and 780034y subseries add an i 2 c bus control function to the m pd78002, 78014, 780024, and 780034 subseries. the m pd78018fy subseries is a version of the m pd78018f subseries with an i 2 c bus control function in the place of the sbi function. in addition, one-time prom, eprom, or flash-memory models m pd78p014, 78p014y (v dd = 2.7 to 6.0 v), m pd78p018f, 78p018fy (v dd = 1.8 to 5.5 v), m pd78f0034, 78f0034y (v dd = 1.8 to 5.5 v), m pd78f0924, 78f0964 (v dd = 2.7 to 5.5 v) that can operate at the same operating voltage as the mask rom models and that are ideal for early and small-scale production of the application system are also available. the block diagram and function outline of each series is shown on the following pages.
4 chapter 1 general figure 1-1. block diagram of m pd78002 subseries remark the internal rom and ram capacities differ depending on the model. to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 intp0/p00- intp3/p03 buz/p36 clock output control pcl/p35 buzzer output interrupt control serial interface 0 watch timer watchdog timer 8-bit timer/ event counter 2 8-bit timer/ event counter 1 78k/0 cpu core rom ram v dd v ss ic0- ic3 system control external access port6 port5 port4 port3 port2 port1 port0 p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 xt1/p04 x2 xt2
5 chapter 1 general table 1-1. functional outline of m pd78002 subseries part number item mask rom 8k bytes 16k bytes 256 bytes 384 bytes 64k bytes 8 bits 8 4 banks 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 53 ? cmos input : 2 ? cmos i/o : 47 (on-chip pull-up resistor on/off selected by software : 47) ? n-ch open drain i/o : 4 ? (15-v withstand, pull-up resistor connected by mask option : 4) ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output: 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, (with main system clock of 10.0 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 2.4 khz, 4.9 khz, 9.8 khz (with main system clock of 10.0 mhz) internal: 5, external: 4 internal: 1 1 internal: 1, external: 1 v dd = 2.7 to 6.0 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) rom high-speed ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port serial interface timer timer output clock output buzzer output vectored maskable interrupt non-maskable source software test input supply voltage operating temperature package internal memory m pd78001b m pd78002b
6 chapter 1 general figure 1-2. block diagram of m pd78002y subseries remark the internal rom and ram capacities differ depending on the model. to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 intp0/p00- intp3/p03 buz/p36 clock output control pcl/p35 buzzer output interrupt control serial interface 0 watch timer watchdog timer 8-bit timer/ event counter 2 8-bit timer/ event counter 1 78k/0 cpu core rom ram v dd v ss ic0- ic3 system control external access port6 port5 port4 port3 port2 port1 port0 p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 xt1/p04 x2 xt2
7 chapter 1 general table 1-2. functional outline of m pd78002y subseries part number item mask rom 8k bytes 16k bytes 256 bytes 384 bytes 64k bytes 8 bits 8 4 banks 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 53 ? cmos input : 2 ? cmos i/o : 47 (on-chip pull-up resistor on/off selected by software : 47) ? n-ch open drain i/o : 4 ? (15-v withstand, pull-up resistor connected by mask option : 4) ? 3-wire serial i/o/sbi/2-wire serial i/o/i 2 c bus mode selectable : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output: 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (with main system clock of 10.0 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 2.4 khz, 4.9 khz, 9.8 khz (with main system clock of 10.0 mhz) internal: 5, external: 4 internal: 1 1 internal: 1, external: 1 v dd = 2.7 to 6.0 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) rom high-speed ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port serial interface timer timer output clock output buzzer output vectored maskable interrupt non-maskable source software test input supply voltage operating temperature package internal memory m pd78001by m pd78002by
8 chapter 1 general figure 1-3. block diagram of m pd78014 subseries remarks 1. the internal rom and ram capacities differ depending on the model. 2. ( ): m pd78p014 to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17- av dd av ss av ref intp0/p00- intp3/p03 buz/p36 clock output control pcl/p35 buzzer output interrupt control a/d converter serial interface 1 serial interface 0 watch timer watchdog timer 8-bit timer/ event counter 2 8-bit timer/ event counter 1 16-bit timer/ event counter 78k/0 cpu core rom ram v dd v ss ic (v pp ) system control external access port6 port5 port4 port3 port2 port1 port0 p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 xt1/p04 x2 xt2
9 chapter 1 general table 1-3. functional outline of m pd78014 subseries (1/2) part number item mask rom prom 8k bytes 16k bytes 24k bytes 32k bytes 32k bytes note 512 bytes 1024 bytes 1024 bytes note 32 bytes 64k bytes 8 bits 8 4 banks 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 53 ? cmos input : 2 ? cmos i/o : 47 (on-chip pull-up resistor on/off selected by software : 47) ? n-ch open drain i/o : 4 (15-v withstand, pull-up resistor connected by mask option : 4) ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 2.7 to 6.0 v ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable : 1 channel ? 3-wire serial i/o mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output: 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (with main system clock of 10.0 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 2.4 khz, 4.9 khz, 9.8 khz (with main system clock of 10.0 mhz) note the internal prom and internal high-speed ram capacities can be changed by using a memory size select register (ims). rom high-speed ram buffer ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output buzzer output internal memory m pd78011b m pd78012b m pd78013 m pd78014 m pd78p014
10 chapter 1 general table 1-3. functional outline of m pd78014 subseries (2/2) part number item internal: 8, external: 4 internal: 1 1 internal: 1, external: 1 v dd = 2.7 to 6.0 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin ceramic shrink dip (750 mil) ( m pd78p014 only) m pd78011b m pd78012b m pd78013 m pd78014 m pd78p014 vectored maskable interrupt non-maskable source software test input supply voltage operating temperature package
11 chapter 1 general figure 1-4. block diagram of m pd78014y subseries remarks 1. the internal rom and ram capacities differ depending on the model. 2. ( ): m pd78p014y to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17 av dd av ss av ref intp0/p00- intp3/p03 buz/p36 clock output control pcl/p35 buzzer output interrupt control a/d converter serial interface 1 serial interface 0 watch timer watchdog timer 8-bit timer/ event counter 2 8-bit timer/ event counter 1 16-bit timer/ event counter 78k/0 cpu core rom ram v dd v ss ic (v pp ) system control external access port6 port5 port4 port3 port2 port1 port0 p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 xt1/p04 x2 xt2
12 chapter 1 general table 1-4. functional outline of m pd78014y subseries (1/2) part number item mask rom prom 8k bytes 16k bytes 24k bytes 32k bytes 32k bytes note 512 bytes 1024 bytes 1024 bytes note 32 bytes 64k bytes 8 bits 8 4 banks 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 53 ? cmos input : 2 ? cmos i/o : 47 (on-chip pull-up resistor on/off selected by software : 47) ? n-ch open drain i/o : 4 (15-v withstand, pull-up resistor connected by mask option : 4) ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 2.7 to 6.0 v ? 3-wire serial i/o/sbi/2-wire serial i/o/i 2 c bus mode selectable : 1 channel ? 3-wire serial i/o mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output: 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (with main system clock of 10.0 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 2.4 khz, 4.9 khz, 9.8 khz (with main system clock of 10.0 mhz) note the internal prom and internal high-speed ram capacities can be changed by using a memory size select register (ims). rom high-speed ram buffer ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output buzzer output internal memory m pd78011by m pd78012by m pd78013y m pd78014y m pd78p014y
13 chapter 1 general table 1-4. functional outline of m pd78014 subseries (2/2) part number item internal: 8, external: 4 internal: 1 1 internal: 1, external: 1 v dd = 2.7 to 6.0 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin ceramic shrink dip (750 mil) ( m pd78p014y only) m pd78011by m pd78012by m pd78013y m pd78014y m pd78p014y vectored maskable interrupt non-maskable source software test input supply voltage operating temperature package
14 chapter 1 general figure 1-5. block diagram of m pd78018f subseries remarks 1. the internal rom and ram capacities differ depending on the model. 2. ( ): m pd78p018f to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17- av dd av ss av ref intp0/p00- intp3/p03 buz/p36 clock output control pcl/p35 buzzer output interrupt control a/d converter serial interface 1 serial interface 0 watch timer watchdog timer 8-bit timer/ event counter 2 8-bit timer/ event counter 1 16-bit timer/ event counter 78k/0 cpu core rom ram v dd v ss ic ( v pp ) system control external access port6 port5 port4 port3 port2 port1 port0 p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 xt1/p04 x2 xt2
15 chapter 1 general table 1-5. functional outline of m pd78018f subseries (1/2) part number item mask rom prom 8k bytes 16k bytes 24k bytes 32k bytes 40k bytes 48k bytes 60k bytes 60k bytes note 1 512 bytes 1024 bytes 1024 bytes note 1 none 512 bytes 1024 bytes 1024 bytes note 2 32 bytes 64k bytes 8 bits 8 4 banks 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 53 ? cmos input : 2 ? cmos i/o : 47 (on-chip pull-up resistor on/off selected by software : 47) ? n-ch open drain i/o : 4 (15-v withstand, pull-up resistor connected by mask option : 4) ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 1.8 to 5.5 v ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable : 1 channel ? 3-wire serial i/o mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output: 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (with main system clock of 10.0 mhz), 32.768 khz (with subsystem clock of 32.768 khz) notes 1. the capacities of the internal prom and internal high-speed ram can be changed by using a memory size select register (ims). 2. the internal expansion ram capacity can be changed by using an internal expansion ram size select register (ixs). rom high-speed ram expansion ram buffer ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output m pd78011f m pd78012f m pd78013f m pd78014f m pd78015f m pd78016f m pd78018f m pd78p018f internal memory
16 chapter 1 general table 1-5. functional outline of m pd78018f subseries (2/2) part number item 2.4 khz, 4.9 khz, 9.8 khz (with main system clock of 10.0 mhz) internal: 8, external: 4 internal: 1 1 internal: 1, external: 1 v dd = 1.8 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic qfp (12 12 mm) ? 64-pin ceramic shrink dip (w/window) (750 mil) : m pd78p018f only ? 64-pin ceramic wqfn (14 14 mm) note : m pd78p018f only note under planning buzzer output vectored maskable interrupt non-maskable source software test input supply voltage operating temperature package m pd78011f m pd78012f m pd78013f m pd78014f m pd78015f m pd78016f m pd78018f m pd78p018f
17 chapter 1 general figure 1-6. block diagram of m pd78018fy subseries remarks 1. the internal rom and ram capacities differ depending on the model. 2. ( ): m pd78p018fy to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17 av dd av ss av ref intp0/p00- intp3/p03 buz/p36 clock output control pcl/p35 buzzer output interrupt control a/d converter serial interface 1 serial interface 0 watch timer watchdog timer 8-bit timer/ event counter 2 8-bit timer/ event counter 1 16-bit timer/ event counter 78k/0 cpu core rom ram v dd v ss ic (v pp ) system control external access port6 port5 port4 port3 port2 port1 port0 p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 xt1/p04 x2 xt2
18 chapter 1 general table 1-6. functional outline of m pd78018fy subseries (1/2) part number item mask rom prom 8k bytes 16k bytes 24k bytes 32k bytes 40k bytes 48k bytes 60k bytes 60k bytes note 1 512 bytes 1024 bytes 1024 bytes note 1 none 512 bytes 1024 bytes 1024 bytes note 2 32 bytes 64k bytes 8 bits 8 4 banks 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 53 ? cmos input : 2 ? cmos i/o : 47 (on-chip pull-up resistor on/off selected by software : 47) ? n-ch open drain i/o : 4 (15-v withstand, pull-up resistor connected by mask option : 4) ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 1.8 to 5.5 v ? 3-wire serial i/o/2-wire serial i/o/i 2 c bus mode selectable : 1 channel ? 3-wire serial i/o mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output: 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (with main system clock of 10.0 mhz), 32.768 khz (with subsystem clock of 32.768 khz) notes 1. the capacities of the internal prom and internal high-speed ram can be changed by using a memory size select register (ims). 2. the internal expansion ram capacity can be changed by using an internal expansion ram size select register (ixs). rom high-speed ram expansion ram buffer ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output m pd78011fy m pd78012fy m pd78013fy m pd78014fy m pd78015fy m pd78016fy m pd78018fy m pd78p018fy internal memory
19 chapter 1 general table 1-6. functional outline of m pd78018fy subseries (2/2) part number item 2.4 khz, 4.9 khz, 9.8 khz (with main system clock of 10.0 mhz) internal: 8, external: 4 internal: 1 1 internal: 1, external: 1 v dd = 1.8 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin ceramic shrink dip (w/window) (750 mil) note : m pd78p018fy only ? 64-pin ceramic wqfn (14 14 mm) note : m pd78p018fy only note under planning buzzer output vectored maskable interrupt non-maskable source software test input supply voltage operating temperature package m pd78011fy m pd78012fy m pd78013fy m pd78014fy m pd78015fy m pd78016fy m pd78018fy m pd78p018fy
20 chapter 1 general figure 1-7. block diagram of m pd780001 to1/p31 ti1/p33 to2/p32 ti2/p34 si1/p20 so1/p21 sck1/p22 ani0-ani7 av dd av ss av ref intp1/p01- intp3/p03 buz/p36 pcl/p35 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer serial interface 1 a/d converter interrupt control buzzer output clock output control 78k/0 cpu core rom (8 k bytes) ram v dd v ss ic port 0 port 2 port 3 port 4 port 5 port 6 p01-p03 p20-p24 p30-p37 p40-p47 p50-p53, p55-p57 p60-p63 p64-p67 system control reset x1 x2
21 chapter 1 general table 1-7. functional outline of m pd780001 function mask rom 8k bytes 192 bytes 64k bytes 8 bits 8 4 banks 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 39 ? cmos input : 4 ? cmos i/o : 35 (pull-up resistor on/off selectable by software : 35) ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 2.7 to 5.5 v ? 3-wire serial i/o mode : 1 channel ? 8-bit timer/event counter : 2 channels ? watchdog timer : 1 channel 2 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (with main system clock of 10.0 mhz) 2.4 khz, 4.9 khz, 9.8 khz (with main system clock of 10.0 mhz) internal: 5, external: 3 internal: 1 1 external: 1 v dd = 2.7 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) rom high-speed ram memory space general-purpose register minimum instruction time instruction set i/o port a/d converter serial interface timer timer output clock output buzzer output vectored maskable interrupt non-maskable source software test input supply voltage operating temperature package internal memory item
22 chapter 1 general figure 1-8. block diagram of m pd780024 subseries remark the internal rom and ram capacities differ depending on the model. 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer watch timer serial interface 30 serial interface 31 uart0 a/d converter interrupt control buzzer output clock output control ti00/to0/p70 ti01/p71 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 si31/p34 so31/p35 sck31/p36 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref buz/p75 pcl/p74 ani0/p10- ani7/p17 intp0/p00- intp3/p03 v dd0 v dd1 v ss0 v ss1 ic 78k/0 cpu core rom ram port 0 p00-p03 port 1 p10-p17 port 2 p20-p25 port 3 p30-p36 port 4 p40-p47 port 5 p50-p57 port 6 p64-p67 port 7 p70-p75 external access system control ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1 xt2
23 chapter 1 general table 1-8. functional outline of m pd780024 subseries part number item mask rom 8k bytes 16k bytes 24k bytes 32k bytes 512 bytes 1024 bytes 64k bytes 8 bits 8 4 banks 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (at 8.38 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 51 ? cmos input : 8 ? cmos i/o : 39 (on-chip pull-up resistor on/off selected by software : 39) ? n-ch open drain i/o : 4 (5-v withstand, pull-up resistor connected by mask option : 4) ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 1.8 to 5.5 v ? 3-wire serial i/o mode : 2 channels ? uart mode : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (8-bit pwm output: 2) 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (with main system clock of 8.38 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 65.5 khz, 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (with main system clock of 8.38 mhz) internal: 13, external: 5 internal: 1 1 v dd = 1.8 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) caution the m pd780024 subseries is under development. rom high-speed ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output buzzer output vectored maskable interrupt non-maskable source software supply voltage operating temperature package internal memory m pd780021 m pd780022 m pd780023 m pd780024
24 chapter 1 general figure 1-9. block diagram of m pd780024y subseries remark the internal rom and ram capacities differ depending on the model. ti00/to0/p70 16-bit timer/ event counter serial interface30 interrupt control buzzer output clock output control uart0 78k/0 cpu core port0 port1 port2 port3 port4 port5 port6 port7 p70-p75 p64-p67 p50-p57 p40-p47 p30-p36 p20-p25 p10-p17 p00-p03 external access system control reset x1 x2 xt1 xt2 rd/p64 wr/p65 wait/p66 astb/p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rom ram a/d converter i 2 c bus v dd0 v dd1 v ss0 v ss1 ic watchdog timer watch timer 8-bit timer/ event counter50 8-bit timer/ event counter51 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref sda0/p32 scl0/p33 buz/p75 pcl/p74 ani0/p10- ani7/p17 intp0/p00- intp3/p03 ti01/p71
25 chapter 1 general table 1-9. functional outline of m pd780024y subseries part number item mask rom 8k bytes 16k bytes 24k bytes 32k bytes 512 bytes 1024 bytes 64k bytes 8 bits 8 4 banks 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (at 8.38 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 51 ? cmos input : 8 ? cmos i/o : 39 (on-chip pull-up resistor on/off selected by software : 39) ? n-ch open drain i/o : 4 (5-v withstand, pull-up resistor connected by mask option : 4) ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 1.8 to 5.5 v ? 3-wire serial i/o mode : 1 channel ? uart mode : 1 channel ?i 2 c bus mode : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (8-bit pwm output: 2) 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (with main system clock of 8.38 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 65.5 khz, 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (with main system clock of 8.38 mhz) internal: 13, external: 5 internal: 1 1 v dd = 1.8 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) caution the m pd780024y subseries is under development. rom high-speed ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output buzzer output vectored maskable interrupt non-maskable source software supply voltage operating temperature package internal memory m pd780021y m pd780022y m pd780023y m pd780024y
26 chapter 1 general figure 1-10. block diagram of m pd780034 subseries remarks 1. the internal rom and ram capacities differ depending on the model. 2. ( ): m pd78f0034 16-bit timer/ event counter 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer watch timer serial interface 30 serial interface 31 uart0 a/d converter interrupt control buzzer output clock output control ti00/to0/p70 ti01/p71 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 si31/p34 so31/p35 sck31/p36 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref buz/p75 pcl/p74 ani0/p10- ani7/p17 intp0/p00- intp3/p03 v dd0 v dd1 v ss0 v ss1 ic ( v pp ) 78k/0 cpu core rom ram port 0 p00-p03 port 1 p10-p17 port 2 p20-p25 port 3 p30-p36 port 4 p40-p47 port 5 p50-p57 port 6 p64-p67 port 7 p70-p75 external access system control ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1 xt2
27 chapter 1 general table 1-10. functional outline of m pd780034 subseries part number item mask rom flash memory 8k bytes 16k bytes 24k bytes 32k bytes 32k bytes note 512 bytes 1024 bytes 1024 bytes note 64k bytes 8 bits 8 4 banks 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (at 8.38 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 51 ? cmos input : 8 ? cmos i/o : 39 (on-chip pull-up resistor on/off selected by software : 39) ? n-ch open drain i/o : 4 (5-v withstand, pull-up resistor connected by mask option : 4) ? 10-bit resolution 8 channels ? low-voltage operation : av dd = 1.8 to 5.5 v ? 3-wire serial i/o mode : 2 channels ? uart mode : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (8-bit pwm output: 2) 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (with main system clock of 8.38 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 65.5 khz, 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (with main system clock of 8.38 mhz) internal: 13, external: 5 internal: 1 1 v dd = 1.8 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) note the capacities of the flash memory and internal high-speed ram can be changed by using a memory size select register (ims). caution the m pd780034 subseries is under development. rom high-speed ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output buzzer output vectored maskable interrupt non-maskable source software supply voltage operating temperature package internal memory m pd780031 m pd780032 m pd780033 m pd780034 m pd78f0034
28 chapter 1 general figure 1-11. block diagram of m pd780034y subseries remarks 1. the internal rom and ram capacities differ depending on the model. 2. ( ): m pd78f0034y ti00/to0/p70 16-bit timer/ event counter serial interface30 interrupt control buzzer output clock output control uart0 78k/0 cpu core port0 port1 port2 port3 port4 port5 port6 port7 p70-p75 p64-p67 p50-p57 p40-p47 p30-p36 p20-p25 p10-p17 p00-p03 external access system control reset x1 x2 xt1 xt2 rd/p64 wr/p65 wait/p66 astb/p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rom ram a/d converter i 2 c bus v dd0 v dd1 v ss0 v ss1 ic (v pp ) watchdog timer watch timer 8-bit timer/ event counter50 8-bit timer/ event counter51 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref sda0/p32 scl0/p33 buz/p75 pcl/p74 ani0/p10- ani7/p17 intp0/p00- intp3/p03 ti01/p71
29 chapter 1 general table 1-11. functional outline of m pd780034y subseries part number item mask rom flash memory 8k bytes 16k bytes 24k bytes 32k bytes 32k bytes note 512 bytes 1024 bytes 1024 bytes note 64k bytes 8 bits 8 4 banks 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (at 8.38 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 51 ? cmos input : 8 ? cmos i/o : 39 (on-chip pull-up resistor on/off selected by software : 39) ? n-ch open drain i/o : 4 (5-v withstand, pull-up resistor connected by mask option : 4) ? 10-bit resolution 8 channels ? low-voltage operation : av dd = 1.8 to 5.5 v ? 3-wire serial i/o mode : 1 channel ? uart mode : 1 channel ?i 2 c bus mode : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (8-bit pwm output: 2) 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (with main system clock of 8.38 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 65.5 khz, 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (with main system clock of 8.38 mhz) internal: 13, external: 5 internal: 1 1 v dd = 1.8 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) note the capacities of the flash memory and internal high-speed ram can be changed by using a memory size select register (ims). caution the m pd780034y subseries is under development. rom high-speed ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output buzzer output vectored maskable interrupt non-maskable source software supply voltage operating temperature package internal memory m pd780031y m pd780032y m pd780033y m pd780034y m pd78f0034y
30 chapter 1 general figure 1-12. block diagram of m pd78014h subseries remark the internal rom and ram capacities differ depending on the model. to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17- av ref intp0/p00- intp3/p03 buz/p36 clock output control pcl/p35 buzzer output interrupt control a/d converter serial interface 1 serial interface 0 watch timer watchdog timer 8-bit timer/ event counter 2 8-bit timer/ event counter 1 16-bit timer/ event counter 78k/0 cpu core rom ram v dd v ss av dd av ss ic system control external access port6 port5 port4 port3 port2 port1 port0 p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p40-p47 p50-p57 p60-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 xt1 x2 xt2
31 chapter 1 general table 1-12. functional outline of m pd78014h subseries part number item mask rom 8k bytes 16k bytes 24k bytes 32k bytes 512 bytes 1024 bytes 32 bytes 64k bytes 8 bits 8 4 banks 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz) 122 m s (at 32.768 khz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 53 ? cmos input : 2 ? cmos i/o : 47 (on-chip pull-up resistor on/off selected by software : 47) ? n-ch open drain i/o : 4 (15-v withstand, pull-up resistor connected by mask option : 4) ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 1.8 to 5.5 v ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable : 1 channel ? 3-wire serial i/o mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output: 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (with main system clock of 10.0 mhz), 32.768 khz (with subsystem clock of 32.768 khz) 2.4 khz, 4.9 khz, 9.8 khz (with main system clock of 10.0 mhz) internal: 8, external: 4 internal: 1 1 internal: 1, external: 1 v dd = 1.8 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) rom high-speed ram buffer ram memory space general-purpose register minimum with main instruction system clock execution with subsystem time clock instruction set i/o port a/d converter serial interface timer timer output clock output buzzer output vectored maskable interrupt non-maskable source software test input supply voltage operating temperature package internal memory m pd78011h m pd78012h m pd78013h m pd78014h
32 chapter 1 general figure 1-13. block diagram of m pd780924 subseries remarks 1. the internal rom and ram capacities differ depending on the model. 2. ( ): m pd78f0924 8-bit timer/ event counter 50 8-bit timer/ event counter 51 8-bit timer/ event counter 52 watchdog timer a/d converter interrupt control real-time output port to50/ti50/p24 ani0/p10- ani7/p17 av dd av ss av ref intp1/p01, intp2/p02 78k/0 cpu core rom ram v dd0 , v dd1 v ss0 , v ss1 test ( v pp ) port0 port1 port2 port3 port4 port5 port6 external access system control p00-p03 p10-p17 p20-p26 p30-p37 p40-p47 p50-p57 p64-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 to51/ti51/p25 to52/ti52/p26 uart00 uart01 rtp0/p30- rtp7/p37 txd00/p21 rxd00/p20 txd01/p23 rxd01/p22 intp0/toff7/p00 intp3/adtrg/p03 real-time pulse unit to70-to75
33 chapter 1 general table 1-13. functional outline of m pd780924 subseries part number item mask rom flash memory 8k bytes 16k bytes 24k bytes 32k bytes 32k bytes note 512 bytes 1024 bytes 1024 bytes note 64k bytes 8 bits 8 4 banks 0.24 m s/0.48 m s/0.96 m s/1.9 m s/3.8 m s (with system clock of 8.38 mhz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 47 ? cmos input : 8 ? cmos i/o : 39 (on-chip pull-up resistor on/off selected by software : 39) ? 8 bits 1 or 4 bits 2 ? 8-bit resolution 8 channels ? low-voltage operation : av dd = 2.7 to 5.5 v ? uart mode : 2 channels ? 8-bit timer/event counter : 3 channels ? 10-bit inverter control timer : 1 channel ? watchdog timer : 1 channel 9 (8-bit pwm output: 3, inverter control output: 6) internal: 12, external: 4 internal: 1 1 v dd = 2.7 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) note the capacities of the flash memory and internal high-speed ram can be changed by using a memory size select register (ims). caution the m pd780924 subseries is under development. rom high-speed ram memory space general-purpose register minimum instruction execution time instruction set i/o port real-time output port a/d converter serial interface timer timer output vectored maskable interrupt non-maskable source software supply voltage operating temperature package internal memory m pd780921 m pd780922 m pd780923 m pd780924 m pd78f0924
34 chapter 1 general figure 1-14. block diagram of m pd780964 subseries remarks 1. the internal rom and ram capacities differ depending on the model. 2. ( ): m pd78f0964 8-bit timer/ event counter 50 8-bit timer/ event counter 51 8-bit timer/ event counter 52 watchdog timer a/d converter interrupt control real-time output port to50/ti50/p24 ani0/p10- ani7/p17 av dd av ss av ref intp1/p01, intp2/p02 78k/0 cpu core rom ram v dd0 , v dd1 v ss0 , v ss1 test ( v pp ) port0 port1 port2 port3 port4 port5 port6 external access system control p00-p03 p10-p17 p20-p26 p30-p37 p40-p47 p50-p57 p64-p67 ad0/p40- ad7/p47 a8/p50- a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 to51/ti51/p25 to52/ti52/p26 uart00 uart01 rtp0/p30- rtp7/p37 txd00/p21 rxd00/p20 txd01/p23 rxd01/p22 intp0/toff7/p00 intp3/adtrg/p03 real-time pulse unit to70-to75
35 chapter 1 general table 1-14. functional outline of m pd780964 subseries part number item mask rom flash memory 8k bytes 16k bytes 24k bytes 32k bytes 32k bytes note 512 bytes 1024 bytes 1024 bytes note 64k bytes 8 bits 8 4 banks 0.24 m s/0.48 m s/0.96 m s/1.9 m s/3.8 m s (with system clock of 8.38 mhz) ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjustment, etc. ? total : 47 ? cmos input : 8 ? cmos i/o : 39 (on-chip pull-up resistor on/off selected by software : 39) ? 8 bits 1 or 4 bits 2 ? 10-bit resolution 8 channels ? low-voltage operation : av dd = 2.7 to 5.5 v ? uart mode : 2 channels ? 8-bit timer/event counter : 3 channels ? 10-bit inverter control timer : 1 channel ? watchdog timer : 1 channel 9 (8-bit pwm output: 3, inverter control output: 6) internal: 12, external: 4 internal: 1 1 v dd = 2.7 to 5.5 v t a = C40 to +85 c ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) note the capacities of the flash memory and internal high-speed ram can be changed by using a memory size select register (ims). caution the m pd780964 subseries is under development. rom high-speed ram memory space general-purpose register minimum instruction execution time instruction set i/o port real-time output port a/d converter serial interface timer timer output vectored maskable interrupt non-maskable source software supply voltage operating temperature package internal memory m pd780961 m pd780962 m pd780963 m pd780964 m pd78f0964
36 chapter 1 general [memo]
37 chapter 2 basics of software chapter 2 basics of software 2.1 data transfer data is exchanged by using an address specified by the de and hl registers as the first address. the number of bytes of the data to be exchanged is specified by the b register. figure 2-1. data exchange (1) registers used a, b, de, hl (2) program list exch: mov a,[de] xch a,[hl] xch a,[de] incw de incw hl dbnz b,$exch ret data exchange address de + b ?1 de address hl + b ?1 hl
38 chapter 2 basics of software 2.2 data comparison data is compared by using an address specified by the de and hl registers as the first address. the number of bytes of the data to be compared is specified by the b register. if the result of comparison is equal, cy is cleared to 0; if not, cy is set to 1. figure 2-2. data comparison (1) registers used a, b, de, hl (2) program list comp: mov a,[de] cmp a,[hl] bnz $error incw de incw hl dbnz b,$comp clr1 cy br rtn error: set1 cy rtn: ret data comparison address de + b ?1 de address hl + b ?1 hl
39 chapter 2 basics of software 2.3 decimal addition the lowest address for decimal addition is specified by the de and hl registers, and the number of digits specified by bytnum is added. the result of the addition is stored to an area specified by the hl register. if an overflow or underflow occurs as a result of the addition, execution branches to error processing. define the branch address as error in the main routine. also declare it as public. figure 2-3. decimal addition (1) flowchart address de + bytnum ?1 de address hl + bytnum ?1 hl address hl + bytnum ?1 hl += decimal subtraction processing bcdadd c ? number of bytes for decimal addition b ? c ?1 number of bytes for decimal addition without sign signs of augend and addend same? decimal addition processing ret bcdad2 no yes
40 chapter 2 basics of software dadds cy ? 0 sign flag sflag ? 0 dadds1 a ? [de] + [hl] + cy adds augend and addend with cy adjusts result to decimal and stores in memory de ? de + 1, hl ? hl + 1 increments addend and augend addresses b ? b ?1 b = 0 a ? [de] + [hl] + cy adds addend and augend with cy yes cy = 1 sign flag sflag ? 1 cy = 0 yes dadds3 result adjusted to decimal? cy = 1 no yes no a7 = 1 no yes sign flag sflag = 1 yes no a7 ? 1 stores a to memory ret dadds6 no error
41 chapter 2 basics of software dsubs makes subtrahend positive sign flag sflag ? 0 makes subtrahend positive sign flag sflag ? 1 a ? [de] ?[hl] ?cy subtracts subtrahend from minuend with cy de ? de + 1, hl ? hl + 1 increments subtrahend and minuend addresses b ? c, cy ? 0 minuend < 0 adjusts result to decimal and stores in memory yes c = 0 inverts sign flag that takes 10's complement yes dsubs1 result = 0 no yes no sign flag = 1 yes no ret dsubs2 c ? c ?1 cy = 1 yes appends negative sign to result dsubs5 no no
42 chapter 2 basics of software (2) registers used ax, bc, de, hl (3) program list ;****************************************************************** ; * ; input parameter * ; hl register: addend first address * ; de register: augend first address * ; output parameter * ; hl register: operation result first address * ; * ;****************************************************************** public bcdadd,bcdad1,bcdad2 public dadds public dsubs extrn error extbit sflag ; bytnum equ 4 ; cseg bcdadd: mov c,#bytnum bcdad1: mov a,c mov b,a dec b bcdad2: mov a,[hl+bytnumC1] xchw ax,de xchw ax,hl xchw ax,de xor a,[hl+bytnumC1] xchw ax,hl xchw ax,de xchw ax,hl bt a.7,$bcdad3 call !dadds ret bcdad3: call !dsubs ret ; error processing branch address ; sign flag ; sets number of digits for operation ; sets number of digits for operation to c register ; loads msb (sign data) of augend ; loads msb (sign data) of augend ; signs coincide? else subtraction processing ; then addition processing
43 chapter 2 basics of software ;============================================================= ; ***** 10 decimal addition ***** ;============================================================= dadds: clr1 cy clr1 sflag dadds1: mov a,[de] addc a,[hl] adjba mov [hl],a incw hl incw de dbnz b,$dadds1 mov a,[de] addc a,[hl] dadds2: bnc $dadds3 set1 sflag clr1 cy dadds3: adjba bnc $dadds4 br error dadds4: bf a.7,$dadds5 br error dadds5: bf sflag,$dadds6 set1 a.7 dadds6: mov [hl],a ret ; starts addition from lowest digit ; end of addition (number of digits for operation C 1) ; negative addition ; then sets negative status ; sets sign
44 chapter 2 basics of software ;================================================================ ; ***** 10 decimal subtraction ***** ;================================================================ dsubs: push hl clr1 sflag mov a,[hl+bytnumC1] clr1 a.7 mov [hl+bytnumC1],a xchw ax,de xchw ax,hl xchw ax,de mov a,[hl+bytnumC1] bf a.7,$dsubs1 clr1 a.7 mov [hl+bytnumC1],a set1 sflag dsubs1: xchw ax,hl xchw ax,de xchw ax,hl mov a,c mov b,a clr1 cy dsubs2: mov a,[de] subc a,[hl] adjbs mov [hl],a incw hl incw de dbnz c,$dsubs2 bnc $dsubs5 pop hl push hl mov a,b mov c,a dsubs3: mov a,#99h sub a,[hl] adjbs mov [hl],a incw hl dbnz c,$dsubs3 pop hl push hl set1 cy mov a,b mov c,a dsubs4: mov a,#0 addc a,[hl] adjba ; sets subtrahend as positive value ; minuend is negative ; then sets minuend as positive value ; sets sign as negative ; end of subtraction of number of digits for operation ; then subtrahend > minuend ; complement operation of result of subtraction ; (result of subtraction C 99h) ; adds 1 to result of complement operation
45 chapter 2 basics of software mov [hl],a incw hl dbnz c,$dsubs4 mov1 cy,sflag not1 cy mov1 sflag,cy ;====================================================== ; ***** 0 check of operation result ***** ;====================================================== dsubs5: mov a,b mov c,a pop hl push hl mov a,#0 dsubs6: cmp a,[hl] incw hl bnz $dsubs7 dbnz c,$dsubs6 pop hl ret dsubs7: bf sflag,$dsubs8 pop hl push hl mov a,[hl+bytnumC1] set1 a.7 mov [hl+bytnumC1],a dsubs8: pop hl ret ; 0 check from lowest digit ; 0 check of all digits completed ; then result of subtraction = 0 ; result of subtraction is negative ; then sets sign
46 chapter 2 basics of software 2.4 decimal subtraction the lowest address for decimal subtraction is specified by the de and hl registers, and the number of digits specified by bytnum is subtracted. the result of the subtraction is stored to an area specified by the hl register. if an overflow or underflow occurs as a result of the subtraction, execution branches to error processing. define the branch address as error in the main routine. also declare it as public. this program replaces minuend and subtrahend with augend and addend, and calls a program of decimal addition. figure 2-4. decimal subtraction (1) flowchart (2) registers used ax, bc, de, hl address de + bytnum ?1 de address hl + bytnum ?1 hl address hl + bytnum ?1 hl ? bcdsub c ? number of bytes for decimal subtraction decimal addition with subtrahend and minuend as addend and augend ret inverts sign bit of subtrahend
47 chapter 2 basics of software (3) program list ;****************************************************************** ; * ; input parameter * ; hl register: subtrahend first address * ; de register: minuend first address * ; output parameter * ; hl register: operation result first address * ; * ;****************************************************************** public bytnum public bcdsub extrn bcdadd,bcdad2 ; bytnum equ 4 ; cseg bcdsub: mov c,#bytnum bcdsu1: mov a,c mov b,a dec b mov a,[hl+bytnumC1] mov1 cy,a.7 not1 cy mov1 a.7,cy mov [hl+bytnumC1],a call !bcdad2 ret ; sets number of digits for operation ; sets number of digits for operation to c register ; sets msb (sign data) of subtrahend for addition ; inverts sign data ; calls decimal addition processing
48 chapter 2 basics of software 2.5 binary-to-decimal conversion binary data of 16 bits in data memory is converted into 5-digit decimal data and stored in data memory. binary data of 16 bits is divided by decimal 10 by the number of times equal to the number of digits (4 times), and conversion is carried out with the result of the operation and the value of the remainder at that time. figure 2-5. binary-to-decimal conversion example to convert ffh into decimal number (1) registers used ax, bc, hl (2) program list public b_dconv datdec equ 10 dseg saddrp rega: ds 2 regb: ds 5 colnum equ 4 b_dconv: movw ax,rega mov b,#colnum movw hl,#regb b_d1: mov c,#datdec divuw c xch a,c mov [hl],a incw hl xch a,c dbnz b,$b_d1 mov a,x mov [hl],a ret 0 00 0 0 low high decimal 5 digits (5 bytes) low binary 16 bits (2 bytes) high 05 5 0 020000 low high decimal 5 digits (5 bytes) ff 0 0 low binary 16 bits (2 bytes) high ; stores binary 16-bit data ; stores decimal 5-digit data
49 chapter 2 basics of software 2.6 bit manipulation instruction a 1 bit of a flag in the data memory is anded with the bit 4 of port 6, and the result is anded with the bit 5 of port 6 and is output to the bit 6 of port 6. figure 2-6. bit operation (1) program list public bit_op,flg bseg flg dbit bit_op: mov1 cy,flg and1 cy,p6.4 or1 cy,p6.5 mov1 p6.6,cy ret flg port6.4 port6.5 port6.6
50 chapter 2 basics of software 2.7 binary multiplication (16 bits 16 bits) data in a multiplicand area (hikake; 16 bits) and multiplier area (kake; 16 bits) are multiplied, and the result is stored in an operation result storage area (kotae). figure 2-7. binary multiplication multiplication is performed by adding the multiplicand by the number of bits of the multiplier that are 1. set the data in the multiplicand (hikake) and multiplier (kake) areas, and call subroutine s_kakeru. extrn s_kakeru extrn hikake,kake,kotae main: hikake=worka (a) hikake+1=worka+1 (a) kake=workb (a) kake+1=workb+1 (a) call !s_kakeru hl=#kotae caution manipulate the data memory in 8-bit units. operation result storage area (4 bytes) kotae + 3 kotae multiplier area (2 bytes) kake + 1 kake multiplicand area (2 bytes) hikake + 1 hikake = ; multiplier ; stores multiplicand data to multiplicand area ; ; stores multiplier data to multiplier area ; ; calls multiplication routine ; hl ? ram address of operation result storage area ; stores result by indirect address transfer
51 chapter 2 basics of software (1) input/output condition ? input parameter hikake : store the multiplicand data in this area. kake : store the multiplier data in this area. ? output parameter kotae : store the result of the operation in this area. (2) spd chart [multiplication subroutine] (3) registers used a, b s_kakeru initializes operation result storage area work1 ? multiplier (low) for (b = #0 ; b < #16 ; b + +) if (b = #8) then work1 ? multiplier (high) shifts work1 1 bit to left if_bit (cy = #1) then adds multiplicand to operation result storage area if (b 1 #15) then shifts operation result stora g e area 1 bit to left
52 chapter 2 basics of software ; multiplicand area ; multiplier area ; work area ; operation result storage area ; ; ; stores multiplier (low) in work area ; initializes operation result storage area ; ; ; ; stores higher multiplier in work area ; if low multiplication is completed ; ; ; shifts multiplier 1 bit to left ; ; ; ; adds multiplicand to operation ; result storage area if carry occurs ; ; ; ; ; ; shifts operation result storage area 1 bit to left ; ; ; ; ; ; (4) program list $pc(014) ; public hikake,s_kakeru,kake,kotae ; ;************************************************ ; ram definition ;************************************************ dseg saddr hikake: ds 2 kake: ds 2 work1: ds 1 kotae: ds 4 ; ;************************************************ ; multiplication ;************************************************ cseg s_kakeru: work1=kake+1 (a) kotae=#0 kotae+1=#0 kotae+2=#0 kotae+3=#0 for(b=#0;b<#16;b++)(a) if(b == #8)(a) work1=kake (a) endif a=work1 clr1 cy rolc a,1 work1=a if_bit(cy) kotae+=hikake (a) (kotae+1)+=hikake+1,cy (a) (kotae+2)+=#0,cy (a) (kotae+3)+=#0,cy (a) endif if(b != #15) (a) kotae+=kotae (a) kotae+1+=kotae+1,cy (a) kotae+2+=kotae+2,cy (a) kotae+3+=kotae+3,cy (a) endif next ret end
53 chapter 2 basics of software 2.8 binary division (32 bits ? 16 bits) data in a dividend area (hiwaru; 32 bits) is divided by data in a divisor area (warum; 16 bits), and the result is stored in an operation result storage area (kotae). if a remainder is generated, it is stored in a calculation result reminder area (amari). if division is executed with the divisor being 0, an error occurs. figure 2-8. binary division the dividend is shifted to the left to the work area starting from the highest digit. if the contents of the work area are greater than the divisor, the divisor is subtracted from the work area, and the least significant bit of the dividend is set to 1. in this way, division is carried out by executing the program by the number of bits of the dividend. if the divisor is 0, an error flag (f_err) is set. dividend storage area (4 bytes) hiwaru + 3 hiwaru calculation result remainder area (2 bytes) amari + 1 amari = operation result storage area (4 bytes) kotae + 3 kotae divisor area (2 bytes) warum + 1 warum ?
54 chapter 2 basics of software set data in the dividend area (hiwaru) and divisor area (warum), and call subroutine s_waru. extrn s_waru extrn hiwaru,warum,kotae exbit f_err main: hiwaru=worka (a) hiwaru+1=worka+1 (a) warum=workb (a) warum+1=workb+1 (a) call !s_waru hl=#kotae if_bit(f_err) calculation error processing endif caution manipulate the data memory in 8-bit units. ; ; ; stores dividend data to dividend area ; ; stores divisor data to divisor area ; ; calls division calculation routine ; hl ? stores ram address of operation result storage area ; ; ; ; ;
55 chapter 2 basics of software (1) input/output conditions ? input parameter hiwaru: store the dividend data in this area. warum : store the divisor data in this area. ? output parameter kotae : store the result of the calculation in this area. (2) spd chart [division subroutine] (3) registers used a, b s_waru clears operation error flag initializes operation result storage area and calculation result remainder area if (divisor = #0) then sets operation error flag if_bit (operation error flag = #0) then for (b = #0 ; b < #32 ; b + +) shifts dividend and calculation result remainder i bit to left at same time if (calculation result remainder divisor) then calculation result remainder ? calculation result remainder - divisor dividend ? dividend or #1 operation result storage area ? dividend area
56 chapter 2 basics of software ; dividend area ; divisor area ; calculation result remainder storage area ; operation error flag ; ; ; clears operation error flag ; clears calculation result storage area to 0 ; ; clears operation result storage area to 0 ; ; ; ; divisor = 0? ; ; sets operation error flag if divisor is 0 ; ; ; operation error? ; starts 32-bit division ; shifts dividend and remainder 1 bit to left ; ; ; ; ; ; ; remainder 3 divisor? ; remainder = remainder C divisor ; ; stores 1 to first bit of dividend area ; ; ; ; ; ; ; ; ; stores operation result ; ; ; ; ; (4) program list $pc(014) ; public s_waru,hiwaru,warum,f_err extrn kotae ; ;************************************************ ; ram definition ;************************************************ dseg saddr hiwaru: ds 4 warum: ds 2 amari: ds 2 bseg f_err dbit ;************************************************ ; division ;************************************************ cseg s_waru: clr1 f_err amari=#0 amari+1=#0 kotae=#0 kotae+1=#0 kotae+2=#0 kotae+3=#0 if(warum == #0) if(warum+1 == #0) set1 f_err endif endif if_bit(!f_err) for(b=#0;b < #32;b++) (a) hiwaru+=hiwaru (a) hiwaru+1+=hiwaru+1,cy (a) hiwaru+2+=hiwaru+2,cy (a) hiwaru+3+=hiwaru+3,cy (a) amari+=amari,cy (a) amari+1+=amari+1,cy (a) if(amari+1 > warum+1) (a) amariC=warum (a) amari+1C=warum+1,cy (a) hiwaru |= #1 elseif_bit(z) if(amari >= warum) (a) amariC=warum(a) amari+1C=warum+1,cy (a) hiwaru |= #1 endif endif next kotae=hiwaru (a) kotae+1=hiwaru+1 (a) kotae+2=hiwaru+2 (a) kotae+3=hiwaru+3 (a) endif ret end
57 chapter 3 application of system clock selection chapter 3 application of system clock selection the 78k/0 series allows you to select a cpu clock and controls the operation of the oscillator by rewriting the contents of the processor clock control register (pcc). when the cpu clock is changed, the time shown in table 3-1 and 3-2 is required since the contents of the pcc have been rewritten until the cpu clock is actually changed. it is therefore not apparent for a while after the contents of the pcc have been rewritten, whether the processor operates on the new or old clock. to stop the main system clock or execute the stop instruction, therefore, the wait time shown in table 3-1 and 3-2 is necessary. table 3-1. maximum time required for changing cpu clock ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 780024, 780024y, 780034, 780034y, 78014h subseries) set value before change set value after change css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 000000010010001101001 0 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions f x /4f xt instructions (77 instructions) 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions f x /8f xt instructions (39 instructions) 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions f x /16f xt instructions (20 instructions) 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions f x /32f xt instructions (10 instructions) 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction f x /64f xt instructions (5 instructions) 1 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction caution do not select dividing the cpu clock (pcc0-pcc2) and changing from the main system clock to subsystem clock (by setting css to 0 ? 1) at the same time. however, dividing the cpu clock (pcc0-pcc2) can be selected at the same time as changing from the subsystem clock to the main system clock. remarks 1. one instruction is the minimum instruction execution time of the cpu clock before change. 2. ( ): f x = 10.0 mhz, f xt = 32.768 khz
58 chapter 3 application of system clock selection table 3-2. maximum time required for changing cpu clock ( m pd780924, 780964 subseries, m pd780001) set value before change set value after change pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 pcc2 pcc1 pcc0 0 00 0 01 0 1 00 1 1 100 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction remark one instruction is the minimum instruction execution time of the cpu clock before change.
59 chapter 3 application of system clock selection figure 3-1. format of processor clock control register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries) r/w css pcc2 pcc1 pcc0 selects cpu clock (f cpu ) 0000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 1000f xt 001 010 011 100 others setting prohibited r cls status of cpu clock 0 main system clock 1 subsystem clock r/w frc selects feedback resistor of subsystem clock 0 uses internal feedback resistor 1 does not use internal feedback resistor r/w mcc controls oscillation of main system clock note 2 0 enables oscillation 1 stops oscillation notes 1. bit 5 is a read-only bit. 2. use mcc to stop the oscillation of the main system clock when the cpu operates on the subsystem clock. do not use the stop instruction. caution be sure to clear bit 3 to 0. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 765432 symbol 10 fffbh pcc0 pcc pcc1 0 pcc2 css cls frc mcc address at reset r/w 04h r/w note1
60 chapter 3 application of system clock selection figure 3-2. format of processor clock control register ( m pd780001) pcc2 pcc1 pcc0 selects cpu clock (f cpu ) 000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 others setting prohibited caution be sure to clear bit 3 to 0. remark f x : main system clock oscillation frequency the fastest instruction of the m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, and m pd780001 is executed in two cpu clocks. therefore, the relation between the cpu clock (f cpu ) and minimum instruction execution time is as shown in table 3-3. table 3-3. relation between cpu clock and minimum instruction execution time ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) cpu clock (f cpu ) minimum instruction execution time: 4/f cpu note except m pd780001 remark f x = 10.0 mhz, f xt = 32.768 khz f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 765432 symbol 10 fffbh pcc0 pcc pcc1 0 pcc2 0 0 0 0 address at reset r/w 04h r/w f x 0.4 m s f x /2 0.8 m s f x /2 2 1.6 m s f x /2 3 3.2 m s f x /2 4 6.4 m s f xt note 122 m s
61 chapter 3 application of system clock selection figure 3-3. format of processor clock control register ( m pd780024, 780024y, 780034, 780034y subseries) css pcc2 pcc1 pcc0 selects cpu clock (f cpu ) 0000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 1000f xt 001 010 011 100 others setting prohibited cls status of cpu clock 0 main system clock 1 subsystem clock frc selects feedback resistor of subsystem clock 0 uses internal feedback resistor 1 does not use internal feedback resistor mcc controls oscillation of main system clock note 2 0 enables oscillation 1 stops oscillation notes 1. bit 5 is a read-only bit. 2. use mcc to stop the oscillation of the main system clock when the cpu operates on the subsystem clock. do not use the stop instruction. caution be sure to clear bit 3 to 0. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 765432 symbol 10 fffbh pcc0 pcc pcc1 0 pcc2 css cls frc mcc address at reset r/w 04h r/w note 1
62 chapter 3 application of system clock selection figure 3-4. format of processor clock control register ( m pd780924, 780964 subseries) pcc2 pcc1 pcc0 selects cpu clock (f cpu ) 000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 others setting prohibited caution be sure to clear bits 3 through 7 to 0. remark f x : main system clock oscillation frequency the fastest instruction of the m pd780024, 780024y, 780034, 780034y, 780924, 780964 subseries is executed in two cpu clocks. therefore, the relation between the cpu clock (f cpu ) and minimum instruction execution time is as shown in table 3-4. table 3-4. relation between cpu clock and minimum instruction execution time ( m pd780024, 780024y, 780034, 780034y, 780924, 780964 subseries) cpu clock (f cpu ) minimum instruction execution time: 2/f cpu note except m pd780924 and 780964 subseries remark f x = 8.38 mhz, f xt = 32.768 khz f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f x 0.24 m s f x /2 0.48 m s f x /2 2 0.96 m s f x /2 3 1.9 m s f x /2 4 3.8 m s f xt /2 note 122 m s 765432 symbol 10 fffbh pcc0 pcc pcc1 0 pcc2 0 0 0 0 address at reset r/w 04h r/w
63 chapter 3 application of system clock selection 3.1 changing pcc immediately after reset when the reset signal is asserted, the slowest mode of the main system clock is selected for the cpu clock. to set the highest speed of the cpu clock, therefore, the contents of the processor clock control register (pcc) must be rewritten. to use the fasted mode, however, the voltage on the v dd pin has to have risen to a sufficient level and be stable. in the following example, the cpu waits until the v dd pin voltage has risen to the sufficient level by using the watch timer (the interval time is set to 3.91 ms). after that, the cpu operates on the fastest clock. figure 3-5. example of selecting cpu clock after reset (1) m pd78014 subseries (2) m pd78018f subseries on off 4.5 v 2.7 v h l commercial power source v dd pin voltage reset signal cpu clock wait time halt status 0.48 s m 7.63 s m 31.3 ms (2 18 /f x : at 8.38 mhz) reset signal is deasserted 10 s after v dd pin voltage has risen to 2.7 v or more. cpu clock oscillation starts. v dd pin voltage has risen to 4.5 v or more before contents of pcc are changed. m 3.9 ms on off 3.5 v 1.8 v h l commercial power source v dd pin voltage reset signal cpu clock wait time halt status 0.48 s m 7.63 s m 31.3 ms (2 18 /f x : at 8.38 mhz) reset signal is deasserted 10 s after v dd pin voltage has risen to 1.8 v or more. cpu clock oscillation starts. v dd pin voltage has risen to 3.5 v or more before contents of pcc are changed. m 3.9 ms
64 chapter 3 application of system clock selection sets watch timer to 3.91 ms while: no watch timer interrupt request ( ! tmif3) clears tmif3 sets pcc in fastest mode (1) spd chart (2) program list ;************************************** ;* sets wait time ;************************************** tmc2=#00110110b while_bit(!tmif3) endw clr1 wtif pcc=#00000000b ; sets watch timer to 3.91 ms ; 3.91 ms? ; sets cpu clock in fastest mode
65 chapter 3 application of system clock selection 3.2 selecting power on/off the 78k/0 series can operate in an ultra low current consumption mode by using the processor clock control register (pcc) and selecting the subsystem clock. by providing a backup power supply such as a ni-cd battery or super capacitor to the system, therefore, the system can continue operating even if a power failure occurs. in this example, a power failure is detected by using intp1 (both the rising and falling edges are selected as the edge to be detected), and the contents of the pcc are changed depending on the port level at that time. figure 3- 6 shows a circuit example, and figure 3-7 shows the system clock changing timing. figure 3-6. example of system clock changing circuit v ss v dd + 5.6 v + intp1/p01 pd78014 m
66 chapter 3 application of system clock selection figure 3-7. example of changing system clock on power on/off (1) m pd78014 subseries (2) m pd78018f subseries on off 6.0 (v) 4.5 (v) commercial power source h l p01/intp1 pin interrupt request occurs 2.7 (v) v dd pin voltage system clock main system clock main system clock subsystem clock interrupt request occurs waits until v dd rises to 4.5 v or more on off 5.5 (v) 3.5 (v) commercial power source h l p01/intp1 pin interrupt request occurs 1.8 (v) v dd pin voltage system clock main system clock main system clock subsystem clock interrupt request occurs waits until v dd rises to 3.5 v or more
67 chapter 3 application of system clock selection ; sets vector address of intp1 ; both edge detection mode ; sets low-speed mode ; sets high-speed mode intp1 if: power off (p01 = low level) then sets cpu clock in slowest mode user processing else sets cpu clock in fastest mode user processing (1) spd chart (2) program list vep0 cseg at 08h dw intp1 mov intm0,#00110000b clr1 pmk1 ei ;***************************************** ;* sets low-/high-speed mode ;***************************************** intp1: if_bit(!p0.1) ; setting of internal hardware (low speed) ; user processing pcc=#10010000b else ; sets internal hardware (high speed) ; user processing pcc=#00000000b endif reti
68 chapter 3 application of system clock selection [memo]
69 chapter 4 applications of watchdog timer chapter 4 applications of watchdog timer the watchdog timer of the 78k/0 series has two modes: watchdog timer mode in which a hang-up of the microcontroller is detected, and interval timer mode. the watchdog timer is set by the following registers: ? timer clock select register 2 (tcl2) : m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001 ? watchdog timer clock select regisrer (wdcs) : m pd780024, 780024y, 780034, 780034y, 780924, 780964 subseries ? watchdog timer mode register (wdtm) caution the format of the registers provided on the m pd780024, 780024y, 780034, 780034y, 780924, and 780964 subseries differs from the format of the registers used in the program examples in this chapter. when using a program example in this chapter with any of the m pd780024, 780024y, 780034, 780034y, 780924, and 780964 subseries, change the setting of the registers according to the registers of the microcontroller used.
70 chapter 4 applications of watchdog timer figure 4-1. format of timer clock select register 2 ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries) caution to change the data of tcl2 except when writing the same data, once stop the timer operation. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. : dont care 4. ( ) : f x = 10.0 mhz or f xt = 32.768 khz 7 tcl27 6 tcl26 5 tcl25 4 tcl24 3 0 2 tcl22 1 tcl21 0 tcl20 symbol tcl2 address ff42h at reset 00h r/w r/w tcl22 0 0 0 0 1 1 1 1 tcl21 0 0 1 1 0 0 1 1 tcl20 0 1 0 1 0 1 0 1 selects count clock of watchdog timer f x /2 4 (625 khz) f x /2 5 (313 khz) f x /2 6 (156 khz) f x /2 7 (78.1 khz) f x /2 8 (39.1 khz) f x /2 9 (19.5 khz) f x /2 10 (9.8 khz) f x /2 12 (2.4 khz) tcl24 0 1 selects count clock of watch timer f x /2 8 (39.1 khz) f xt (32.768 khz) 0 1 1 1 1 0 0 1 1 0 1 0 1 selects frequency of buzzer output disables buzzer output f x /2 10 (9.8 khz) f x /2 11 (4.9 khz) f x /2 12 (2.4 khz) setting prohibited tcl27 tcl26 tcl25
71 chapter 4 applications of watchdog timer figure 4-2. format of timer clock select register 2 ( m pd780001) caution to change the data of tcl2 except when writing the same data, once stop the timer operation. remarks 1. f x : main system clock oscillation frequency 2. : dont care 3. ( ) : f x = 10.0 mhz tcl27 tcl26 tcl25 0 0 tcl22 tcl21 tcl20 tcl2 76543210 symbol address at reset r/w ff42h 00h r/w tcl22 tcl21 tcl20 0 0 0 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 1 0 1 selects count clock of watchdog timer f x /2 4 (625 khz) f x /2 5 (313 khz) f x /2 6 (156 khz) f x /2 7 (78.1 khz) f x /2 8 (39.1 khz) f x /2 9 (19.5 khz) f x /2 10 (9.8 khz) f x /2 12 (2.4 khz) tcl27 0 tcl26 tcl25 1 1 0 0 0 1 1 1 1 1 0 1 selects frequency of buzzer output disables buzzer output f x /2 10 (9.8 khz) f x /2 11 (4.9 khz) f x /2 12 (2.4 khz) setting prohibited
72 chapter 4 applications of watchdog timer figure 4-3. format of watchdog timer clock select register ( m pd780024, 780024y, 780034, 780034y, 780924, 780964 subseries) wdcs2 wdcs1 wdcs0 overflow time of watchdog timer/interval timer 00 0 2 12 /f x (489 m s) 00 1 2 13 /f x (978 m s) 01 0 2 14 /f x (1.96 ms) 01 1 2 14 /f x (3.91 ms) 10 0 2 16 /f x (7.82 ms) 10 1 2 17 /f x (15.6 ms) 11 0 2 18 /f x (31.3 ms) 11 1 2 20 /f x (125 ms) remarks 1. f xx : main system clock oscillation frequency 2. (): f x = 8.38 mhz 7 0 6 0 5 0 4 0 3 0 2 wdcs2 1 wdcs1 0 wdcs0 symbol wdcs address ff42h at reset 00h r/w r/w
73 chapter 4 applications of watchdog timer figure 4-4. format of watchdog timer mode register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) notes 1. once wdtm3 and wdtm4 have been set to 1, they cannot be cleared to 0 by software. 2. when run is set to 1, the wdtm starts interval timer operation. 3. once run has been set to 1, it cannot be cleared to 0 by software. therefore, when counting has been started, it cannot be stopped by any means other than the reset signal. cautions 1. when run is set to 1 and the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the timer clock select register 2 (tcl2). 2. when using the watchdog timer modes 1 and 2, confirm that the interrupt request flag (tmif4) is 0 and then set wdtm4 to 1. if wdtm4 is set to 1 while tmif4 is 1, the non-maskable interrupt occurs regardless of the contents of wdtm3. remark : dont care 765432 symbol 10 wdtm4 selects operation mode of watchdog timer note 1 fff9h 0 wdtm 0 wdtm3 0 wdtm4 0 0 run address at reset r/w 00h r/w wdtm3 0 interval timer mode (maskable interrupt note 2 request occurs when overflow occurs) 1 watchdog timer mode 1 (non-maskable interrupt request occurs when overflow occurs) 0 1 watchdog timer mode 2 (reset operation starts when overflow occurs) 1 run selects watchdog timer operation note 3 0 stops counting 1 clears counter and starts counting
74 chapter 4 applications of watchdog timer figure 4-5. format of watchdog timer mode register ( m pd780024, 780024y, 780034, 780034y subseries) notes 1. once wdtm3 and wdtm4 have been set to 1, they cannot be cleared to 0 by software. 2. once run has been set to 1, it cannot be cleared to 0 by software. therefore, when counting has been started, it cannot be stopped by any means other than the reset signal. caution when run is set to 1 and the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the watchdog timer clock select register (wdcs). remark : dont care 765432 symbol 10 wdtm4 selects operation mode of watchdog timer note 1 fff9h 0 wdtm 0 wdtm3 0 wdtm4 0 0 run address at reset r/w 00h r/w wdtm3 0 interval timer mode (maskable interrupt request occurs when overflow occurs) 1 watchdog timer mode 1 (non-maskable interrupt request occurs when overflow occurs) 0 1 watchdog timer mode 2 (reset operation starts when overflow occurs) 1 run selects watchdog timer operation note 2 0 stops counting 1 clears counter and starts counting
75 chapter 4 applications of watchdog timer figure 4-6. format of watchdog timer mode register ( m pd780924, 780964 subseries) notes 1. once wdtm3 and wdtm4 have been set to 1, they cannot be cleared to 0 by software. 2. when run is set to 1, the wdtm starts interval timer operation. 3. once run has been set to 1, it cannot be cleared to 0 by software. therefore, when counting has been started, it cannot be stopped by any means other than the reset signal. caution when run is set to 1 and the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the watchdog timer clock select register (wdcs). remark : dont care 765432 symbol 10 wdtm4 selects operation mode of watchdog timer note 1 , controls interrupt of timer, and reset by watchdog timer fff9h 0 wdtm 0 wdtm3 0 wdtm4 0 0 run address at reset r/w 00h r/w wdtm3 0 interval timer mode note 2 (maskable interrupt request occurs when overflow occurs) 1 watchdog timer mode 1 (non-maskable interrupt request occurs when overflow occurs) the pwm output off function of tm7 can be used with intwdt. 0 1 watchdog timer mode 2 (reset operation starts when overflow occurs) the pwm output off function of tm7 can be used with intwdt. 1 run selects watchdog timer operation note 3 0 stops counting 1 clears counter and starts counting
76 chapter 4 applications of watchdog timer 4.1 setting watchdog timer mode reset processing or non-maskable interrupt processing is performed after the watchdog timer has detected a hang- up. you can select which processing is to be performed by the watchdog timer mode register (wdtm). when the watchdog timer mode is used, the timer must be cleared at intervals shorter than the set hang-up detection time. if the timer is not cleared, an overflow occurs, and reset or interrupt processing is executed. the hang-up detection time of the watchdog timer is set by the timer clock select register 2 (tcl2). in the following example, the hang-up detection time is set to 7.82 ms and the reset processing is performed when an overflow occurs. (1) spd chart (2) program list ;************************************* ;* sets watchdog timer ;************************************* tcl2=#00000100b wdtm=#10011000b ; user processing 1 set1 run ; user processing 2 set1 run ; user processing 3 set1 run ; sets watchdog timer to 7.82 ms ; sets reset start mode ; clears timer ; clears timer ; clears timer - - - - - - - - - - - - - - sets hang-up detection time of watchdog timer to 7.82 ms sets watchdog timer in reset start mode user processing 1 clears watchdog timer user processing 2 clears watchdog timer user processing 3 clears watchdog timer
77 chapter 4 applications of watchdog timer 4.2 setting interval timer mode when the interval timer mode is used, the interval time is set by the timer clock select register 2 (tcl2) (interval time = 0.488 ms to 125 ms). in this mode, an interrupt request flag (tmif4) is set when an overflow occurs in the timer. in the following example, three types of times, 0.977 ms, 7.82 ms, and 125 ms, are set. figure 4-7. count timing of watchdog timer (1) program list <1> to set 0.977 ms tcl2=#00000001b ; sets 0.977 ms wdtm=#10001000b ; selects interval timer mode <2> to set 7.82 ms tcl2=#00000100b ; sets 7.82 ms wdtm=#10001000b ; selects interval timer mode <3> to set 125 ms tcl2=#00000111b ; sets 125 ms wdtm=#10001000b ; selects interval timer mode timer count intwdt fc fd fe ff 00 01 02 03 fd fe ff 00
78 chapter 4 applications of watchdog timer [memo]
79 chapter 5 applications of 16-bit timer/event counter chapter 5 applications of 16-bit timer/event counter the 16-bit timer/event counter of the 78k/0 series has the following six functions: ? interval timer ? pwm output ( m pd78014, 78014y, 78018f, 78018fy, and 78014h subseries only) ? pulse width measurement ? external event counter ? square wave output ? one-shot pulse output ( m pd780024, 780024y, 780034, and 780034y subseries only) the 16-bit timer/event counter is set by the following registers: < m pd78014, 78014y, 78018f, 78018fy, 78014h subseries> ? timer clock select register 0 (tcl0) ? 16-bit timer mode control register (tmc0) ? capture/compare control register 0 (crc0) ? 16-bit timer output control register (toc0) ? port mode register 3 (pm3) ? external interrupt mode register (intm0) ? sampling clock select register (scs) < m pd780024, 780024y, 780034, 780034y subseries> ? 16-bit timer mode control register (tmc0) ? capture/compare control register 0 (crc0) ? 16-bit timer output control register (toc0) ? prescaler mode register (prm0) ? port mode register 7 (pm7) caution the format of the registers provided on the m pd780024, 780024y, 780034, and 780034y subseries differs from the format of the registers used in the program examples in this chapter. when using a program example in this chapter with any of the m pd780024, 780024y, 780034, and 780034y subseries, change the setting of the registers according to the registers of the microcontroller used.
80 chapter 5 applications of 16-bit timer/event counter figure 5-1. format of timer clock select register 0 ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) cautions 1. set the valid edge of the ti0/intp0 pin by the external interrupt mode register (intm0). the frequency of the sampling clock is selected by the sampling clock select register (scs). 2. to enable pcl output, set tcl00 through tcl03, and then set cloe to 1 by using a 1-bit memory manipulation instruction. 3. read the count value from tm0, not from the capture/compare register 01(cr01), when ti0 is specified as the count clock of tm0. 4. before writing new data to tcl0, stop the timer operation once. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. ti0 : input pin of 16-bit timer/event counter 4. tm0 : 16-bit timer register 5. ( ) : at f x = 10.0 mhz or f xt = 32.768 khz others 7 cloe 6 tcl06 5 tcl05 4 tcl04 3 tcl03 2 tcl02 1 tcl01 0 tcl00 symbol tcl0 address ff40h at reset 00h r/w r/w tcl06 0 0 0 1 tcl05 0 1 1 0 tcl04 0 0 1 0 selects count clock of 16-bit timer register ti0 (valid edge can be specified) f x /2 (5.0 mhz) f x /2 2 (2.5 mhz) f x /2 3 (1.25 mhz) setting prohibited cloe 0 1 controls pcl output disables output enables output tcl03 0 0 1 1 1 1 1 tcl02 0 1 0 0 0 0 1 tcl01 0 1 0 0 1 1 0 selects clock of pcl output f xt (32.768 khz) f x /2 3 (1.25 mhz) f x /2 4 (625 khz) f x /2 5 (313 khz) f x /2 6 (156 khz) f x /2 7 (78.1 khz) f x /2 8 (39.1 khz) setting prohibited tcl00 0 1 0 1 0 1 0 others
81 chapter 5 applications of 16-bit timer/event counter figure 5-2. format of 16-bit timer mode control register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) ovf0 detects overflow of 16-bit timer register 0 overflow does not occur 1 overflow occurs tmc03 tmc02 tmc01 selects operation mode selects output timing of to0 occurrence of and clear mode interrupt request cautions 1. before setting the clear mode or changing the output timing of to0, stop the timer operation (by clearing tmc01 through tmc03 to 0, 0, 0). 2. set the valid edge of the ti0/intp0 pin by the external interrupt mode register (intm0). the frequency of the sampling clock is selected by the sampling clock select register (scs). 3. when using the pwm mode, set data to cr00 after setting the pwm mode. 4. when a mode in which the timer is cleared and started on coincidence between tm0 and cr00, the ovf0 flag is set to 1 when the set value of cr00 is ffffh and the value of tm0 changes from ffffh to 0000h. remarks 1. to0 : output pin of 16-bit timer/event counter 2. ti0 : input pin of 16-bit timer/event counter 3. tm0 : 16-bit timer register 4. cr00 : compare register 00 stops operation (clears tm0 to 0) pwm mode (free running) free running mode clears and starts at valid edge of ti0 clears and start at coinci- dence between tm0 and cr00 not affected pwm pulse output coincidence between tm0 and cr00 coincidence between tm0 and cr00, or valid edge of ti0 coincidence between tm0 and cr00 coincidence between tm0 and cr00 or valid edge of ti0 coincidence between tm0 and cr00 coincidence between tm0 and cr00 or valid edge of ti0 does not occur occurs if tm0 and cr00 coincide 765432 symbol 10 ff48h ovf0 tmc0 tmc01 tmc03 tmc02 0 0 0 0 address at reset r/w 00h r/w 000 001 010 011 100 101 110 111
82 chapter 5 applications of 16-bit timer/event counter figure 5-3. format of 16-bit timer mode control register ( m pd780024, 780024y, 780034, 780034y subseries) ovf0 detects overflow of 16-bit timer register 0 overflow does not occur 1 overflow occurs tmc03 tmc02 tmc01 selects operation mode selects output timing of to0 occurrence of and clear mode interrupt request 000 001 010 011 100 101 110 111 cautions 1. before setting the clear mode or changing the output timing of to0, stop the timer operation (by clearing tmc02 and tmc03 to 0, 0). 2. set the valid edge of the ti00/to0/p70 pin by the prescaler mode register 0 (prm0). the frequency of the sampling clock is selected by the sampling clock select register (scs). 3. when a mode in which the timer is cleared and started on coincidence between tm0 and cr00, the ovf0 flag is set to 1 when the set value of cr00 is ffffh and the value of tm0 changes from ffffh to 0000h. remarks 1. to0 : output pin of 16-bit timer/event counter 2. ti00 : input pin of 16-bit timer/event counter 3. tm0 : 16-bit timer register 4. cr00 : compare register 00 5. cr01 : compare regisrer 01 stops operation (clears tm0 to 0) free running mode clears and starts at valid edge of ti00 clears and start at coinci- dence between tm0 and cr00 not affected coincidence between tm0 and cr00 or between tm0 and cr01 coincidence between tm0 and cr00, or between tm0 and cr01, or valid edge of ti00 coincidence between tm0 and cr00 or between tm0 and cr01 coincidence between tm0 and cr00, or between tm0 and cr01, or valid edge of ti00 coincidence between tm0 and cr00 or between tm0 and cr01 coincidence between tm0 and cr00, or between tm0 and cr01, or valid edge of ti00 does not occur occurs if tm0 and cr00 coincide and if tm0 and cr01 coincide 765432 symbol 10 ff60h ovf0 tmc0 tmc01 tmc03 tmc02 0 0 0 0 address at reset r/w 00h r/w
83 chapter 5 applications of 16-bit timer/event counter figure 5-4. format of 16-bit timer output control register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) cautions 1. be sure to stop the timer operation before setting toc0. 2. lvs0 and lvr0 are always 0 when they are read immediately after data has been set. 765432 symbol 10 toe0 controls output of 16-bit timer/event counter ff4eh toe0 toc0 toc01 lvs0 lvr0 0 0 0 0 address at reset r/w 00h r/w 0 disables output (port mode) 1 enables output toc01 pwm mode other than pwm mode selects active level controls timer output f/f 0 active high disables reverse operation 1 active low enables reverse operation lvs0 sets status of timer output f/f of 16-bit timer/ event counter 0 not affected 0 resets timer output f/f (to 0) lvr0 0 1 1 sets timer output f/f (to 1) 1 setting prohibited 0 1
84 chapter 5 applications of 16-bit timer/event counter figure 5-5. format of 16-bit timer output control register ( m pd780024, 780024y, 780034, 780034y subseries) cautions 1. be sure to stop the timer operation before setting toc0 (except ospt). 2. lvs0 and lvr0 are always 0 when they are read immediately after data has been set. 3. ospt is automatically cleared after data has been set. it is therefore always 0 when read. 765432 symbol 10 toe0 controls output of timer 0 ff63h toe0 toc0 toc01 lvs0 lvr0 toc04 ospe ospt 0 address at reset r/w 00h r/w 0 disables output (port mode) 1 enables output toc01 controls timer output f/f on coincidence between cr00 and tm0 0 disables reverse operation 1 enables reverse operation lvs0 sets status of timer output f/f of timer 0 0 not affected 0 resets timer output f/f (to 0) lvr0 0 1 1 sets timer output f/f (to 1) 1 setting prohibited 0 1 toc04 controls timer output f/f on coincidence between cr01 and tm0 0 disables reverse operation 1 enables reverse operation ospe controls one-shot pulse output operation 0 successive pulse output 1 one-shot pulse output ospt controls output trigger of one-shot pulse by software 0 no one-shot pulse trigger 1 one-shot pulse trigger
85 chapter 5 applications of 16-bit timer/event counter figure 5-6. format of port mode register 3 ( m pd78014, 78014y, 78018, 78018fy, 78014h subseries) caution when using the p30/to0 pin as a timer output, set the output latch of pm30 and p30 to 0. figure 5-7. format of external interrupt mode register ( m pd78014, 78014y, 78018, 78018fy, 78014h subseries) caution before setting the valid edge of the intp0 pin, clear bits 1 through 3 (tmc01 through tmc03) of the 16-bit timer mode control register (tmc0) to 0, 0, 0, and stop the timer. 765432 symbol 10 es11 selects valid edge of intp0 ffech 0 intm0 0 es11 es10 es20 es21 es30 es31 address at reset r/w 00h r/w 0 falling edge 0 rising edge es10 0 1 1 setting prohibited 1 both rising and falling edges 0 1 es21 selects valid edge of intp1 0 falling edge 0 rising edge es20 0 1 1 setting prohibited 1 both rising and falling edges 0 1 es31 selects valid edge of intp2 0 falling edge 0 rising edge es30 0 1 1 setting prohibited 1 both rising and falling edges 0 1 765432 symbol 10 pm3n selects input/output mode of p3n pin (n = 0-7) ff23h pm30 pm3 pm31 pm33 pm32 pm34 pm35 pm36 pm37 address at reset r/w ffh r/w 0 output mode (output buffer on) 1 input mode (output buffer off)
86 chapter 5 applications of 16-bit timer/event counter figure 5-8. format of sampling clock select register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) caution f x /2 n+1 is the clock supplied to the cpu, and f x /2 6 and f x /2 7 are the clocks supplied to the peripheral hardware. f x /2 n+1 is stopped in the halt mode. remarks 1. n : value (n = 0 to 4) set to the bits 0 through 2 (pcc0 through pcc2) of the processor clock control register (pcc) 2. f x : main system clock oscillation frequency 3. ( ) : at f x = 10.0 mhz figure 5-9. format of capture/compare control register 0 ( m pd780024, 780024y, 780034, 780034y subseries) cautions 1. be sure to stop the timer operation before setting crc0. 2. when a mode in which the timer is cleared and started on coincidence between tm0 and cr00 is selected by the 16-bit timer mode control register (tmc0), do not specify cr00 as the capture register. 765432 symbol 10 scs1 selects sampling clock of intp0 ff47h scs0 scs scs1 00 0 0 0 0 address at reset r/w 00h r/w scs0 0 f x /2 n+1 0 0 setting prohibited 1 1 f x /2 6 (156 khz) 0 1 f x /2 7 (78.1 khz) 1 765432 symbol 10 crc00 selects operation mode of cr00 ff62h crc00 crc0 crc01 0 crc02 0 0 0 0 address at reset r/w 04h r/w 0 operates as compare register 1 operates as capture register crc01 selects capture trigger of cr00 0 captures at valid edge of ti01 1 captures at valid edge of ti00 crc02 selects operation mode of cr01 0 operates as compare register 1 operates as capture register
87 chapter 5 applications of 16-bit timer/event counter figure 5-10. format of prescaler mode register 0 ( m pd780024, 780024y, 780034, 780034y subseries) caution when setting the valid edge of ti00 for the count clock, do not set clear & start mode by the valid edge of ti00, and do not set ti00 for the capture trigger. remarks 1. f x : main system clock oscillation frequency 2. ti00, ti01 : input pin of 16-bit timer/event counter 3. ( ) : at f x = 8.38 mhz figure 5-11. format of port mode register 7 ( m pd780024, 780024y, 780034, 780034y subseries) 765432 symbol 10 prm01 selects count clock ff61h prm00 prm0 prm01 00 es10 es01 es10 es11 address at reset r/w 00h r/w 0 f x (8.38 mhz) 0 f x /2 2 (2.09 mhz) prm00 0 1 1 f x /2 6 (131 khz) 1 ti00 valid edge 0 1 es01 selects valid edge of ti00 0 falling edge 0 rising edge es00 0 1 1 setting prohibited 1 both rising and falling edges 0 1 es11 selects valid edge of ti01 0 falling edge 0 rising edge es10 0 1 1 setting prohibited 1 both rising and falling edges 0 1 765432 symbol 10 pm7n selects input/output mode of p7n pin (n = 0-5) ff27h pm70 pm7 pm71 pm73 pm72 pm74 pm75 1 1 address at reset r/w ffh r/w 0 output mode (output buffer on) 1 input mode (output buffer off)
88 chapter 5 applications of 16-bit timer/event counter 5.1 setting of interval timer to set the 16-bit timer/event counter as an interval timer, first set the timer clock select register 0 (tcl0) and the 16-bit timer mode control register (tmc0). the clear mode of the 16-bit timer is set by tmc0 and the interval time is set by tcl0. after that, set the value of the compare register (cr00) from the setup time and count clock. determine the setup time by using the following expression: setup time = (compare register value + 1) count clock cycle this section shows two examples of setup times of the interval timer: 10 ms and 50 ms. (a) interval of 10 ms <1> setting of tmc0 selects a mode in which the timer is cleared and started on coincidence between tm0 and cr00. <2> setting of tcl0 select the f x /2 mode in which an interval time of 10 ms or more can be set and the resolution is the highest. <3> setting of cr00 10 ms = (n + 1) n = 10 ms 8.38 mhz/2 C 1 = 4.1899 (1) program list cr00 = #41899 tcl0 = #00100000b ; selects count clock f x /2 tmc0 = #00001100b ; clears and starts 16-bit timer/event counter when tm0 and cr00 coincide (b) interval of 50 ms <1> setting of tmc0 selects a mode in which the timer is cleared and started on coincidence between tm0 and cr00. <2> setting of tcl0 select the f x /2 3 mode in which an interval time of 50 ms or more can be set and the resolution is the highest. <3> setting of cr00 50 ms = (n + 1) n = 50 ms 8.38 mhz/2 3 C 1 = 52374 (1) program list cr00 = #52374 tcl0 = #01000000b ; selects count clock f x /2 3 tmc0 = #00001100b ; clears and starts 16-bit timer/event counter when tm0 and cr00 coincide 1 8.38 mhz/2 ? ? 1 8.38 mhz/2 3 ? ?
89 chapter 5 applications of 16-bit timer/event counter 5.2 pwm output when using the 16-bit timer/event counter in the pwm output mode, set the pwm mode by the 16-bit timer mode control register (tmc0) and enables the output of the 16-bit timer/event counter by the 16-bit timer output control register (toc0). the pulse width (active level) of pwm is determined by the value set to the compare register 00 (cr00). because the pwm of the 78k/0 series has a resolution of 14 bits, however, bits 2 through 15 of cr00 are valid (clear bits 0 and 1 of cr00 to 0, 0). in the example below, the basic cycle of the pwm mode is set to 61.0 m s (2/f x 2 8 ) and the low level is selected as the active level. the high-order 4 bits of the pulse width are rewritten depending on the value of the parameter (00h to ffh). therefore, in the following application example, pwm output can be performed in 16 steps (cr00 = 0ffch to fffch). (1) description of package pwm : pwm output subroutine name pwmout: input parameter of pwm active level ax name usage attribute bytes pwmout sets pwm active level saddr 1 1 level 2 bytes ? 16-bit timer/event counter ? p30/to0 ? setting of 16-bit timer/event counter pwm output mode tmc0 = #00000010b pwm basic cycle: 61.0 m s tcl0 = #00100000b low-active output toc0 = #00000011b ? p30 output mode pm30 = 0 ? p30 output latch p30 = 0 after setting data to pwmout in ram, call subroutine pwm.
90 chapter 5 applications of 16-bit timer/event counter (2) example of use extrn pwm, pwmout toc0 = #00000011b ; sets low-active pwm output tcl0 = #00100000b ; selects count clock f x /2 tmc0 = #00000010b ; sets pwm mode pwmout = a ; sets input parameter of active level call !pwm (3) spd chart (4) program list public pwm,pwmout pwm_dat dseg saddr pwmout: ds 1 ;************************************ ;* pwm output (16 steps) ;************************************ p0_seg cseg pwm: a=pwmout a<<=1 a<<=1 a<<=1 a<<=1 a|=#0fh x=#0fch cr00=ax ret . . . . . . pwm loads data of pwmout decodes data of high-order 4 bits of cr00 sets xffch to cr00 ( x: 0 to fh ) ; pwm output data area (0-15) ; loads high-order data of pwmout ; sets low-order 12 bits to 0ffch
91 chapter 5 applications of 16-bit timer/event counter 5.3 remote controller signal reception this section introduces two examples of programs of the m pd78014 subseries that receives signals from a remote controller by using the 16-bit timer/event counter. ? the counter is cleared each time the valid edge of the remote controller signal has been detected, and measures a pulse width from the timer count value (capture register cr01) when the next valid edge has been detected. ? the timer operates in the free running mode to measure a pulse width from the difference of the counter between valid edges. pwm output is also performed at the same time. the remote controller signal is received by a pin receiver diode and is input to the p00/intp0 pin via receive amplifier m pc1490. figure 5-12 shows an example of a remote controller signal receiver circuit, and figure 5-13 shows the format of the remote controller signal. figure 5-12. example of remote controller signal receiver circuit ph310 160 k w f 0 v cc 100 k w in + out + 100 f m intp0/p00 v dd gnd 4.7 w in + 1 f m c d + 10 f m gnd c 1 1000 pf pc1490 m pd78014 m +5 v shield case
92 chapter 5 applications of 16-bit timer/event counter figure 5-13. remote controller signal transmitter ic output signal because the receiver preamplifier m pc1490 used in the circuit example on the previous page is low-active, the level input to the m pd78014 subseries is the inverted data of the remote controller transmit data. figure 5-14. output signal of receiver preamplifier time at oscillation frequency of 455 khz first time second time and onward (signal transmitted only while key is held down) 67.5 ms 108 ms 108 ms 9 ms 13.5 ms 27 ms 27 ms 67.5 ms 9 ms 4.5 ms 13.5 ms 2.25 ms 9 ms 2.25 ms 11.25 ms 0.56 ms 1.125 ms 01 1001 0.56 ms leader code 4.5 ms custom code 8 bits custom code 8 bits data code 8 bits data code 8 bits pc1490 output 4.5 ms leader code m 9 ms h l
93 chapter 5 applications of 16-bit timer/event counter 5.3.1 remote controller signal reception by counter clearing table 5-1 shows the valid pulse width for receiving a remote controller signal in the program example shown in this section, and <1> through <6> describes how to process each signal. the repeat signal of the remote controller signal is valid only within 250 ms after a valid signal has been input. if a signal input within 3 ms after the normal data has been loaded, the data is invalid. table 5-1. valid time of input signal signal name output time valid time leader code (low) 9 ms 6.8 ms-11.8 ms leader code normal 4.5 ms 3 ms-5 ms (high) repeat 2.25 ms 1.8 ms-3 ms custom/data 0 1.125 ms 0.5 ms-1.8 ms code 1 2.25 ms 1.8 ms-2.5 ms <1> leader code (low) the interval time of the 16-bit timer/event counter is set to 1.5 ms, and the port level is sampled by means of interrupt processing. when five low levels have been detected in succession, these low levels are identified as a leader code, and the interval time is changed to 7.81 ms. after that, the pulse width of the low level of the leader code is measured by using rising-edge interrupt request intp0. figure 5-15. sampling of remote controller signal interval time noise noise valid if low five times in succession 7.81 ms 1.5 ms
94 chapter 5 applications of 16-bit timer/event counter <2> leader code (high) the pulse width while the leader code is high is measured by using the falling-edge interrupt request intp0 and the count value of the timer. <3> custom/data code the pulse width of each 1 bit (1 cycle) is measured by using the falling-edge interrupt request intp0. after the data of the 32nd bit has been loaded, the system tests if the inverted data and custom code coincide. it also checks that there is no data in the 33rd bit. <4> repeat code detection when the high level of the leader code is less than 3 ms, the pulse width from output of the leader code to the rising edge of the intp0 is measured. <5> valid period of repeat code after the valid data has been input, sampling is performed by the interrupt processing (1.5 ms interval) of the 16-bit timer/event counter to measure the valid time of the repeat code of 250 ms. <6> time out during pulse width measurement if the interrupt request of the 16-bit timer/event counter (7.81 ms) occurs during pulse width measure- ment, it is judged to be time out, and the data is invalid. (1) description of package rmdata : stores remote controller receive data rpt : repeat valid period identification flag ipdtfg : valid data identification flag rmdtok : input signal validity identification flag rmdtset : input signal identification flag bank 0: ax, bc, hl
95 chapter 5 applications of 16-bit timer/event counter name usage attribute bytes rptct repeat code valid time counter saddr 1 rmendct no-input time counter after data input selmod mode selection ld_ct leader signal detection counter rmdata valid data storage area workp input signal storage area saddrp 4 name usage ipdtfg presence/absence of valid data rmdtok validity of input signal rmdtset presence/absence of input signal rpt judgment whether repeat valid period elapsed 5 levels 12 bytes ? 16-bit timer/event counter ? p00/intp0 ? setting of 16-bit timer/event counter clears timer on coincidence between tm0 and cr00 tmc0 = #00001100b count clock f x /2 tcl0 = #00100000b compare register 00 cr00 = #6290 ? intp0 sampling clock f x /2 7 scs = #00000011b ? intp0 high-priority interrupt ppr0 = 0 ? enables 16-bit timer/event counter interrupt tmmk0 = 0 ? defines custom code to be cstm and declares public ? ram clear started by intp0 and inttm0 interrupt requests
96 chapter 5 applications of 16-bit timer/event counter (2) example of use public cstm extrn rmdata,rptct extbit rpt,rmdtset,ipdtfg cstm equ 9dh cr00=#6290 tcl0=#00100000b tmc0=#00001100b scs=#00000011b clr1 ppr0 clr1 rpt clr1 ipdtfg clr1 rmdtset clr1 tmmk0 ei dt_test: if_bit(rmdtset) clr1 rmdtset if_bit(rpt) ; ; repeat processing ; else ; ; processing when there is input ; endif else if_bit(!rpt) ; ; processing when there is no input ; endif endif ; remote controller custom code ; sets 1.5 ms ;f x /128 as intp0 sampling clock ; intp0 with high priority ; clears flag ; enables timer interrupt
97 chapter 5 applications of 16-bit timer/event counter inttm00 selects register bank 1 enables master interrupt if: input signal exists (ipdtfg) if: valid data exists (rmdtok) then then if: no input within repeat valid time (250 ms) then invalidates repeat code else clears rpt, ipdtfg, and rmdtok counts repeat valid time counts leader low time s_lowct else if: no input after end of data input (within 4.5 ms) then valid data exists sets rmdtok and rmdtset sets leader low detection mode s_m0set initializes leader low detection counter else counts leader low time s_lowct s_lowct if: leader low detection mode then if: p00 = low if: p00 = low five times in succession then then selects leader low measuring mode sets 16-bit timer to 7.81 ms sets intp0 rising-edge detection mode enables intp0 initializes leader low detection counter initializes leader detection counter else else sets leader low detection mode s_m0set initializes leader detection counter (3) spd chart
98 chapter 5 applications of 16-bit timer/event counter intp0 selects register bank 0 waits for 100 s wait m case: selmod of: 1 leader low measuring mode lead_l of: 2 leader high measuring mode lead_h of: 3 custom code/data loading mode cdcode of: 4 repeat code detection mode repcd of: 5 abnormal data detection mode endchk lead_l if: p00 = high lead_h if: p00 = low waits for 100 s wait then m if: p00 = high then reads timer cr_read if: 6.8 ms ieader low 11.8 ms then selects leader high detection mode sets intp0 falling-edge detection mode else sets leader low detection mode s_m0set then waits for 100 s wait m if: p00 = low then reads timer cr_read if: 2 ms leader high 5 ms then if: ieader high 3 3 ms then selects custom code/data load mode initializes data storage area else selects repeat detection mode sets intp0 rising-edge detection mode else sets leader low detection mode s _ m0set
99 chapter 5 applications of 16-bit timer/event counter cdcode if: p00 = low then waits for 100 s wait m if: p00 = low then reads timer cr_read if: 0.5 ms < input data 2.5 ms then if: input data 3 1.8 ms then sets cy else clears cy stores cy to data storage area if: end of 32 bits of data input then if: custom code coincides then if: custom/data code coincides with inverted data then stores data code sets status in which input data exists sets ipdtfg and clears rmdtset, rpt, and rmdtok sets leader low detection mode s_m0set else sets leader low detection mode s_m0set else sets leader low detection mode s_m0set else sets leader low detection mode s_m0set repcd if: p00 = high then waits for 100 s wait m if: p00 = high then if: valid data exists then reads timer cr_read if: repeat code 1 ms then sets repeat code valid status sets rpt sets data input end status sets abnormal data detection mode s_m5set else sets leader low detection mode s_m0set else sets abnormal data detection mode s m5set
100 chapter 5 applications of 16-bit timer/event counter endchk if: p00 = low then waits for 100 s wait m if: p00 = low then sets input signal invalid status sets leader low detection mode s_m0set clears ipdtfg and rpt cr_read reads capture register stops 16-bit timer operation starts timer s_m0set selects leader low detection mode disables intp0 interrupt sets 16-bit timer to 1.5 ms s_m5set selects abnormal data detection mode sets counter for repeat valid time sets 16-bit timer to 1.5 ms
101 chapter 5 applications of 16-bit timer/event counter ; repeat code valid time counter ; no-input time counter after data input ; selects mode ; leader signal detection counter ; valid data storage area ; input signal storage area ; valid data exists ; input signal is valid ; input signal exists ; repeat code valid period ; sets vector address of intp0 ; sets vector address of 16-bit timer ; enables interrupt (intp0) ; input signal exists? ; valid data exists? ; repeat invalid time ; repeat code invalid status ; sets that valid data exists ; sets leader (low) detection mode (4) program list public rpt,ipdtfg,rmdtok,rmdtset public rmendct,rptct,selmod,ld_ct,rmdata extrn cstm rm_dat dseg saddr rptct: ds 1 rmendct: ds 1 selmod: ds 1 ld_ct: ds 1 rmdata: ds 1 rm_datp dseg saddrp workp: ds 4 bseg ipdtfg dbit rmdtok dbit rmdtset dbit rpt dbit vep0 cseg at 06h dw intp0 vetm0 cseg at 14h dw inttm0 ;****************************************************** ; remote controller signal timer processing ;****************************************************** tm0_seg cseg inttm0: sel rb1 ei if_bit(ipdtfg) if_bit(rmdtok) rptct C C if(rptct==#0) clr1 rpt clr1 ipdtfg clr1 rmdtok endif call !s_lowct else rmendct C C if(rmendct==#0) set1 rmdtok set1 rmdtset call !s_m0set endif ld_ct=#5 endif else call !s_lowct endif reti
102 chapter 5 applications of 16-bit timer/event counter s_lowct: if(selmod==#0) if_bit(!p0.0) ld_ct C C if(ld_ct==#0) selmod=#1 tmc0=#00000000b cr00=#32767 tmc0=#00001100b intm0=#00000100b clr1 pif0 clr1 pmk0 ld_ct=#5 endif else ld_ct=#5 endif else call !s_moset ld_ct=#5 endif ret $eject ;*********************************************************** ;* remote controller signal edge detection processing ;*********************************************************** p0_seg cseg intp0: sel rb0 call !wait switch(selmod) case 1: call !lead_l break case 2: call !lead_h break case 3: call !cdcode break case 4: call !repcd break case 5: call !endchk ends ret1 ; leader (low) detection mode? ; leader (low) measuring mode ; timer: 7.81 ms ; enables intp0 interrupt ; sets leader (low) detection mode ; waits for 100 m s ; leader low detection processing ; leader high detection processing ; custom/data code loading processing ; repeat code detection processing ; abnormal data detection processing
103 chapter 5 applications of 16-bit timer/event counter ; level check p0.0 = 0: noise ; waits for 100 m s ; reads timer value ; 6.8 ms C (1.5 ms * 4) ; 11.8 ms C (1.5 ms * 5) ; leader high detection mode ; intp0 falling edge ; sets leader (low) detection mode ; sets leader (low) detection mode ; level check p0.0 = 1: noise ; waits for 100 m s ; reads timer value ; 1.8 ms C 100 m s * 2 C 160 clocks (edge detection ? timer starts) ; 5 ms C 100 m s * 2 C 160 clocks (edge detection ? timer starts) ; custom/data code (3 ms C 100 m s * 2)? ; data loading mode ; initializes work area ; sets most significant bit to 1 (to check end of data) ; repeat detection mode ; intp0 rises ; sets leader (low) detection mode ; sets leader (low) detection mode ;**************************************** ;* leader low detection ;**************************************** lead_l: if_bit(p0.0) call !wait if_bit(p0.0) call !cr_read if(ax>=#3354) if(ax<#18035) selmod=#2 intm0=#00000000b else call !s_moset endif else call !s_moset endif endif endif ret $eject ;**************************************** ;* leader high detection ;**************************************** lead_h: if_bit(!p0.0) call !wait if_bit(!p0.0) call !cr_read if(ax>=#6710C160/2) if(ax<#20132C160/2) if(ax>#11743C160/2) selmod=#3 workp=#0000h (workp)+2=#8000h else selmod=#4 intm0=#00000100b endif else call !s_m0set endif else call !s_m0set endif endif endif ret $eject
104 chapter 5 applications of 16-bit timer/event counter ; level check p0.0 = 1: noise ; waits for 100 m s ; reads timer value ; 0.5 ms C 100 m s * 2 C 190 clocks (edge detection ? timer starts) ; 2.5 ms C 100 m s * 2 C190 clocks (edge detection ? timer starts) ; 1.8 ms C 100 m s * 2 C 190 clocks (edge detection ? timer starts) ; sets work area address ; sets number of digits of work area ; stores 1-bit data ; shifts 1 bit ; end of shifting all bits ; end of 32-bit input? ; custom code check ; custom code inverted data check ; data code inverted data check ; stores input data ; sets status in which input data exists ; sets leader (low) detection mode ; sets leader (low) detection mode ;****************************** ;* custom/data code loading ;****************************** cdcode: if_bit(!p0.0) call !wait if_bit(!p0.0) call !cr_read if(ax>=#1257C190/2) if(ax<#9646C190/2) if(ax>=#6710C190/2) set1 cy else clr1 cy endif hl=#workp+3 c=#4 wkshft: a=[hl] rorc a,1 [hl]=a hl C C dbnz c,$wkshft if_bit(cy) if(workp+0==#cstm) (a) a^workp+1 if(a==#0ffh) a=workp+2 a^=workp+3 if(a==#0ffh) rmdata=workp+2 (a) set1 ipdtfg clr1 rmdtset clr1 rpt clr1 rmdtok call !s_m5set else call !s_m0set endif else call !s_m0set endif else call !s_m0set
105 chapter 5 applications of 16-bit timer/event counter ; sets leader (low) detection mode ; sets leader (low) detection mode ; level check p0.0 = 0: noise ; waits for 100 m s ; valid data exists? ; reads timer value ; 1 ms C 100 m s * 2 C 190 clocks (edge detection ? timer starts) ; input signal check after end of data ; sets leader (low) detection mode ; sets leader (low) detection mode endif endif else call !s_m0set endif else call !s_m0set endif endif endif ret $eject ;************************************ ;* repeat code detection ;************************************ repcd: if_bit(p0.0) call !wait if_bit(p0.0) if_bit(rmdtok) call !cr_read if(ax<=#3354C190/2) set1 rpt clr1 rmdtok clr1 rmdtset call !s_m5set else call !s_m0set endif else call !s_m0set endif endif endif ret $eject
106 chapter 5 applications of 16-bit timer/event counter ;**************************************** ;* abnormal data detection ;**************************************** endchk: if_bit(!p0.0) call !wait if_bit(!p0.0) clr1 ipdtfg clr1 rpt call !s_m0set endif endif ret ;**************************************** ;* waits for 100 m s ;**************************************** wait: b=#(838C14C12C8)/12 waitct: dbnz b,$waitct ret ;***************************************** ;* sets leader (low) detection mode ;***************************************** s_m0set: tmc0=#00000000b cr00=#6290 tcl0=#00100000b tmc0=#00001100b selmod=#0 set1 pmk0 ret ;***************************************** ;* sets abnormal data detection mode ;***************************************** s_m5set: rptct=#173 selmod=#5 rmendct=#3 tmc0=#00000000b cr00=#6290 tmc0=#00001100b ret ;**************************************** ;* reads timer count value ;**************************************** cr_read: ax=cr01 tmc0=#00000000b tmc0=#00001100b ret ; level check p0.0 = 1: noise ; waits for 100 m s ; abnormal data input ; input signal invalid ; sets leader (low) detection mode ; call(14), ret(12), mov(8) ; sets 100 m s ; 1 instruction 12 clocks ; sets timer to 1.5 ms ; leader (low) detection mode ; 250 ms measuring counter ; data input end mode ; no-input checking counter ; stops operation ; sets 1.5 ms ; stops operation ; starts timer
107 chapter 5 applications of 16-bit timer/event counter 5.3.2 remote controller signal reception by pwm output and free running mode ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries only) table 5-2 shows the valid pulse width when a remote controller signal is received by this program. <1> through <6> below describes how each signal is processed. table 5-2. valid time of input signal signal name output time valid time leader code (low) 9 ms 3 ms-10 ms leader code normal 4.5 ms 3 ms-5 ms (high) repeat 2.25 ms 1.8 ms-3 ms custom/data 0 1.125 ms 0.5 ms-1.8 ms code 1 2.25 ms 1.8 ms-2.5 ms <1> leader code (low) the value of the capture register (cr01) is stored to memory by an interrupt request that occurs when the falling edge of intp0 is detected. the pulse width is measured from the difference between the values of cr01 and the compare register (cr00) when the rising edge is generated. <2> leader code (high) the pulse width between the high levels of the leader code is measured by the falling-edge interrupt request intp0 and the count value of the timer. <3> custom/data code the pulse width of each 1 bit (1 cycle) is measured by the falling-edge interrupt request intp0. after the data of the 32nd bit has been loaded, the system tests if the inverted data and custom code coincide. it also checks that there is no data of the 33rd bit. <4> repeat code detection when the high level of the leader code is less than 3 ms, the pulse width from output of the leader code to the rising edge of the intp0 is measured. <5> valid period of repeat code after the valid data has been input, the overflow flag (ovf0) of the 16-bit timer/event counter is tested by the main program, and the repeat code valid time of 250 ms is measured. <6> time out during pulse width measurement the ovf0 of the 16-bit timer/event counter is tested during pulse width measurement. if it is detected two times, time out is assumed and the data is assumed to be invalid. because the 16-bit timer/event counter operates in the pwm mode in this example, the remote controller signal is received and, at the same time, pwm output can be performed by linking the program of 5.2 pwm output.
108 chapter 5 applications of 16-bit timer/event counter (1) description of package tim_pro : name of subroutine processing timer overflow rmdata : stores remote controller receive data rpt : repeat valid period identification flag ipdtfg : valid data identification flag rmdtok : valid input signal identification flag rmdtset : input signal identification flag ovsens : intp0 processing timer overflow detection flag bank 0: ax, bc, hl name usage attribute bytes rptct repeat code invalid time counter saddr 1 rmendct no-input time counter after data input selmod mode selection ld_ct leader signal detection counter rmdata valid data storage area to_cnt timer overflow detection counter cr01_np newest timer count value storage area saddrp 2 cr01_op previous timer count value storage area workp input signal storage area 4 name usage ipdtfg presence/absence of valid data rmdtok presence/absence of valid input signal rmdtset presence/absence of input signal rpt judgment whether repeat valid period elapsed to_flg occurrence of timer overflow ovsens detection of timer overflow by intp0 processing
109 chapter 5 applications of 16-bit timer/event counter 5 levels 11 bytes ? 16-bit timer/event counter ? p00/intp0 ? p30/to0 ? setting of 16-bit timer/event counter pwm output mode tmc0 = #00000010b pwm basic cycle: 61.0 m s tcl0 = #00100000b low-active output toc0 = #00000011b ? p30 output mode pm30 = 0 ? intp0 sampling clock f x /2 7 scs = #00000011b ? intp0 high-priority interrupt ppr0 = 0 ? enables intp0 interrupt pmk0 = 0 ? defines custom code to cstm and declares public ? ram clear ? test the ovf0 of the 16-bit timer/event counter. when ovf0 is set, call subroutine tim_pro. ? start by an interrupt request when the valid edge of the remote controller signal is detected.
110 chapter 5 applications of 16-bit timer/event counter ; custom code ; pwm output, low active setting ; selects count clock f x /2 ; pwm mode, overflow occurs ; intp0 falling edge ; intp0 sampling clock f x /128 ; intp0 with high priority ; clears flag ; enables intp0 interrupt ; detects timer overflow by intp0 processing ; timer overflow occurs (2) example of use public cstm extrn rmdata,rptct,pwm,pwmout,tim_pro extbit rpt,rmdtset,ipdtfg,to_flg,ovsens cstm equ 9dh toc0=#00000011b tcl0=#00100000b tmc0=#00000010b intm0=#00000000b scs=#00000011b clr1 ppr0 clr1 rpt clr1 ipdtfg clr1 rmdtset clr1 pmk0 ei dt_test: if_bit(ovsens) clr1 ovsens call !tim_pro elseif_bit(ovf0) clr1 ovf0 set1 to_flg call !tim_pro endif if_bit(rmdtset) clr1 rmdtset if_bit(rpt) ; ; repeat processing ; else ; ; processing when input exists ; endif else if_bit(!rpt) ; ; processing when input does not exist ; endif endif mov pwmout,a call !pwm
111 chapter 5 applications of 16-bit timer/event counter (3) spd chart tim_pro if: input signal exists to_chk if: leader low detection mode then else if: valid data exists then if: repeat code invalid time then sets repeat code invalid status clears rpt, ipdtfg, rmdtok checks timer overflow to_chk if: no input exists after input of data (within 61.0 s 2) m then sets that valid data exists sets rmdtok, rmdtset sets leader low detection mode s_m0set else checks timer overflow to_chk then sets that timer overflow does not occur else timer overflow count if: timer overflow occurs 2 times then sets leader low detection mode s_m0set intp0 selects register bank 0 waits for 100 s wait m case: selmod of: 0 leader low detection mode rm_sta of: 1 leader low measuring mode lead_l of: 2 leader high measuring mode lead_h of: 3 custom code/data loading mode cdcode of: 4 repeat code detection mode repcd of: 5 abnormal data detection mode endchk
112 chapter 5 applications of 16-bit timer/event counter rm_sta if: p00 = low then waits for 100 s wait m if: p00 = low then stores data of capture register to memory selects leader low measuring mode 1 sets intp0 rising-edge detection mode lead_l if: p00 = high lead_h if: p00 = low waits for 100 s wait then m if: p00 = high then reads timer pw_ct if: 3 ms ieader low 10 ms then selects leader high detection mode sets intp0 falling-edge detection mode else sets leader low detection mode s_m0set then waits for 100 s wait m if: p00 = low then reads timer pw_ct if: 2 ms leader high 5 ms then if: ieader high 3 3 ms then selects custom code/data loading mode initializes data storage area else selects repeat detection mode sets intp0 rising-edge detection mode else sets leader low detection mode s_m0set
113 chapter 5 applications of 16-bit timer/event counter cdcode if: p00 = low then waits for 100 s wait m if: p00 = low then reads timer cr_read if: 0.5 ms < input data 2.5 ms then if: input data 3 1.8 ms then sets cy else clears cy stores cy to data storage area if: end of 32 bits of data input then if: custom code coincidence then if: coincidence between custom/data code and inverted data then stores data code sets input data existing status sets ipdtfg, and clears rmdtset, rpt, and rmdtok sets abrormal data detection mode s_m5set else sets leader low detection mode s_m0set else sets leader low detection mode s_m0set else sets leader low detection mode s_m0set repcd if: p00 = high then waits for 100 s wait m if: p00 = high then if: valid data exists then reads timer pw_ct if: repeat code 1 ms then sets repeat code valid status sets rpt sets data input end status sets abnormal data detection mode s_m5set else sets leader low detection mode s_m0set else sets abnormal data detection mode s_m5set
114 chapter 5 applications of 16-bit timer/event counter endchk if: p00 = low then waits for 100 s wait m if: p00 = low then sets input signal invalid status sets leader low detection mode s_m0set clears ipdtfg, rpt pw_ct if: ovf occurs after edge detection processing then if: ovf occurs < interrupt acknowledgment processing time (65 clocks) then sets that timer overflow occurs loads capture register value subtracts capture register value from previous value if: borrow occurs as result of subtraction (cy = 1) then if: timer overflow occurs (to_flg = 1) then clears cy flag else if: timer overflow occurs (to_flg = 1) then sets cy flag stores capture register value to memory s_m0set selects leader low detection mode clears to_flg sets intp0 falling-edge detection mode s_m5set selects abnormal data detection mode sets repeat valid time counter
115 chapter 5 applications of 16-bit timer/event counter ; repeat code valid time counter ; no-input time counter after data input ; mode selection ; leader signal detection counter ; valid data storage area ; timer overflow counter ; newest timer counter value storage area ; previous timer counter value storage area ; input signal storage area ; valid data exists ; input signal valid ; input signal exists ; repeat code valid period ; timer overflow occurs ; detects timer overflow by intp0 processing ; sets vector address of intp0 ; input signal exists? ; valid data exists? ; repeat invalid time ; repeat code valid status ; valid data exists ; sets leader (low) detection mode ; checks timer overflow (4) program list public tim_pro,rpt,ipdtfg,rmdtok,rmdtset public rmendct,rptct,selmod,ld_ct,rmdata public to_flg,ovsens extrn cstm rm_dat dseg saddr rptct: ds 1 rmendct:ds 1 selmod: ds 1 ld_ct: ds 1 rmdata: ds 1 to_cnt: ds 1 rm_datp dseg saddrp cr01_np:ds 2 cr01_op:ds 2 workp: ds 4 bseg ipdtfg dbit rmdtok dbit rmdtset dbit rpt dbit to_flg dbit ovsens dbit vep0 cseg at 06h dw intp0 $eject ;****************************************************** ; remote controller signal timer processing ;****************************************************** tm0_seg cseg tim_pro: if_bit(ipdtfg) if_bit(rmdtok) rptct C C if(rptct==#0) clr1 rpt clr1 ipdtfg clr1 rmdtok endif else rmendct C C if(rmendct==#0) set1 rmdtok set1 rmdtset call !s_m0set endif endif else call !to_chk endif ret
116 chapter 5 applications of 16-bit timer/event counter ; sets start edge detection mode ; waits for 100 m s ; start edge detection processing ; leader low detection processing ; leader high detection processing ; custom/data code loading processing ; repeat code detection processing ; abnormal data detection processing ; starts timer count ; level check p0.0 = 1: noise ; waits for 100 m s ; stores capture register ; leader low detection mode ; intp0 rising edge to_chk: if(selmod==#0) clr1 to_flg else to_cnt++ if(to_cnt==#2) call !s_m0set endif endif ret $eject ;*********************************************************** ;* remote controller signal edge detection processing ;*********************************************************** p0_seg cseg intp0: sel rb0 call !wait switch(selmod) case 0: call !rm_sta break case 1: call !lead_l break case 2: call !lead_h break case 3: call !cdcode break case 4: call !repcd break case 5: call !endchk ends ret1 ;*********************************************************** ;* start edge detection ;*********************************************************** rm_sta: clr1 to_flg if_bit(!p0.0) call !wait if_bit(!p0.0) cr01_op=cr01 (ax) selmod=#1 intm0=#00000100b to_cnt=#0 endif endif ret
117 chapter 5 applications of 16-bit timer/event counter ;**************************************** ;* leader low detection ;**************************************** lead_l: if_bit(p0.0) call !wait if_bit(p0.0) call !pw_ct if_bit(!cy) to_cnt=#0 if(ax>=#12582) if(ax<#41942) selmod=#2 intm0=#00000000b else call !s_m0set endif else call !s_m0set endif else call !s_m0set endif endif endif ret $eject ;**************************************** ;* leader high detection ;**************************************** lead_h: if_bit(!p0.0) call !wait if_bit(!p0.0) call !pw_ct if_bit(!cy) to_cnt=#0 if(ax>=#7549) if(ax<#20971) if(ax>#12582) selmod=#3 workp=#0000h (workp)+2=#8000h else selmod=#4 intm0=#00000100b endif else call !s_m0set endif else call !s_m0set endif else call !s_m0set endif endif endif ret $eject ; level check p0.0 = 1: noise ; waits for 100 m s ; reads timer value ;3 ms ; 10 ms ; leader high detection mode ; intp0 falling edge ; sets start edge detection mode ; sets start edge detection mode ; sets start edge detection mode ; level check p0.0 = 0: noise ; waits for 100 m s ; reads timer value ; 1.8 ms ;5 ms ; custom/data code (3 ms)? ; data loading mode ; initializes work area ; sets most significant bit to 1 (to confirm end of data) ; repeat detection mode ; intp0 rises ; sets start edge detection mode ; sets start edge detection mode ; sets start edge detection mode
118 chapter 5 applications of 16-bit timer/event counter ;****************************** ;* custom/data code loading ;****************************** cdcode: if_bit(!p0.0) call !wait if_bit(!p0.0) call !pw_ct if_bit(!cy) to_cnt=#0 if(ax>=#2096) if(ax<#10485) if(ax>=#7549) set1 cy else clr1 cy endif hl=#workp+3 c=#4 wkshft: a=[hl] rorc a,1 [hl]=a hl C C dbnz c,$wkshft if_bit(cy) if(workp+0==#cstm) (a) a^=workp+1 if(a==#0ffh) a=workp+2 a^=workp+3 if(a==#0ffh) rmdata=workp+2 (a) set1 ipdtfg clr1 rmdtset clr1 rpt clr1 rmdtok call !s_m5set else call !s_m0set endif else call !s_m0set endif else call !s_m0set endif endif else call !s_m0set endif else ; level check p0.0 = 1: noise ; waits for 100 m s ; reads timer value ; 0.5 ms ; 2.5 ms ; 1.8 ms ; sets work area address ; sets number of work area digits ; stores 1-bit data ; shifts 1 bit ; end of shifting all digits ; end of input of 32 bits? ; checks custom code ; checks custom code inverted data ; checks data code inverted data ; stores input data ; sets input data existing status ; sets start edge detection mode ; sets start edge detection mode ; sets start edge detection mode
119 chapter 5 applications of 16-bit timer/event counter call !s_m0set endif else call !s_m0set endif endif endif ret $eject ;************************************ ;* repeat code detection ;************************************ repcd: if_bit(p0.0) call !wait if_bit(p0.0) if_bit(rmdtok) call !pw_ct if_bit(!cy) to_cnt=#0 if(ax<=#4193) set1 rpt clr1 rmdtok clr1 rmdtset call !s_m5set else call !s_m0set endif else call !s_m0set endif else call !s_m0set endif endif endif ret $eject ; sets start edge detection mode ; sets start edge detection mode ; level check p0.0 = 1: noise ; waits for 100 m s ; valid data? ; reads timer value ;1 ms ; checks input signal after end of data ; sets start edge detection mode ; sets start edge detection mode ; sets start edge detection mode
120 chapter 5 applications of 16-bit timer/event counter ; level check p0.0 = 1: noise ; waits for 100 m s ; abnormal data input ; input signal invalid ; sets start edge detection mode ; ovf0 after edge detection? ; interrupt acknowledgment processing time = 65 clocks (max) ; loads capture register value ; ax = cr01_np C cr01_op ; saves operation result ; cr01_np > cr01_op ; timer overflow occurs (flag test) ; normal data ; timer overflow ; error occurs ; restores operation result ;********************************************* ;* abnormal data detection ;********************************************* endchk: if_bit(!p0.0) call !wait if_bit(!p0.0) clr1 ipdtfg clr1 rpt call !s_m0set endif endif ret ;********************************************* ;* calculation of capture register value ;********************************************* pw_ct: if_bit(ovf0) if(cr01<#10000C33) (ax) clr1 ovf0 set1 ovsens set1 to_flg endif endif cr01_np=cr01 (ax) a=cr01_np+0 aC=cr01_op x=a a=cr01_np+1 subc a,cr01_op+1 bc=ax if_bit(cy) if_bit(to_flg) clr1 cy endif else if_bit(to_flg) set1 cy endif endif cr01_op=cr01_np (ax) ax=bc clr1 to_flg ret
121 chapter 5 applications of 16-bit timer/event counter ;********************************************** ;* waits for 100 m s ;********************************************** wait: b=#(838C14C12C8)/12 waitct: dbnz b,$waitct ret ;********************************************** ;* sets start edge detection mode ;********************************************** s_m0set: to_cnt=#0 selmod=#0 intm0=#00000000b ret ;********************************************** ;* setting of abnormal data detection mode ;********************************************** s_m5set: rptct=#16 selmod=#5 rmendct=#2 ret ; call (14), ret (12), mov (8) ; sets 100 m s ; 1 instruction 12 clocks ; start edge detection mode ; intp0 falling edge ; 250 ms measuring counter ; data input end mode ; no-input checking counter
122 chapter 5 applications of 16-bit timer/event counter [memo]
123 chapter 6 applications of 8-bit timer/event counter chapter 6 applications of 8-bit timer/event counter the 8-bit timer/event counter of the 78k/0 series has the following functions: ? interval timer ? external event counter ? square wave output ? pwm output ( m pd780024, 780024y, 780034, 780034y, 780924, and 780964 subseries only) two channels or three channels of 8-bit timers/event counters are provided and these timers/event counters can be used as a 16-bit timer/event counter when connected in cascade. the 8-bit timers/event counters are set by the following registers: < m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001> ? timer clock select register 1 (tcl1) ? 8-bit timer mode control register (tmc1) ? 8-bit timer output control register (toc1) ? port mode register 3 (pm3) ? port 3 (p3) < m pd780024, 780024y, 780034, 780034y subseries> ? timer clock select register 50, 51 (tcl50, tcl51) ? 8-bit timer mode control register 50, 51 (tmc50, tmc51) ? port mode register (pm7) < m pd780924, 780964 subseries> ? timer clock select register 50, 51, 52 (tcl50, tcl51, tcl52) ? 8-bit timer mode control register 50, 51, 52 (tmc50, tmc51, tmc52) caution the format of the registers provided on the m pd780024, 780024y, 780034, 780034y, 780924, and 780964 subseries differs from the format of the registers used in the program examples in this chapter. when using a program example in this chapter with any of the m pd780024, 780024y, 780034, 780034y, 780924, and 780964 subseries, change the setting of the registers according to the registers of the microcontroller used.
124 chapter 6 applications of 8-bit timer/event counter figure 6-1. format of timer clock select register 1 ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) caution before writing new data to tcl1, stop the timer operation once. remarks 1. f x : main system clock oscillation frequency 2. ti1 : input pin of 8-bit timer register 1 3. ti2 : input pin of 8-bit timer register 2 4. ( ) : at f x = 10.0 mhz 7 tcl17 6 tcl16 5 tcl15 4 tcl14 3 tcl13 2 tcl12 1 tcl11 0 tcl10 symbol tcl1 address ff41h at reset 00h r/w r/w tcl13 0 0 0 0 1 1 1 1 1 1 1 1 tcl12 0 0 1 1 0 0 0 0 1 1 1 1 tcl11 0 0 1 1 0 0 1 1 0 0 1 1 selects count clock of 8-bit timer register 1 falling edge of ti1 rising edge of ti1 f x /2 2 (2.5 mhz) f x /2 3 (1.25 mhz) f x /2 4 (625 khz) f x /2 5 (313 khz) f x /2 6 (156 khz) f x /2 7 (78.1 khz)) f x /2 8 (39.1 khz) f x /2 9 (19.6 khz) f x /2 10 (9.8 khz) f x /2 12 (2.4 khz) setting prohibited tcl10 0 1 0 1 0 1 0 1 0 1 0 1 others tcl17 0 0 0 0 1 1 1 1 1 1 1 1 tcl16 0 0 1 1 0 0 0 0 1 1 1 1 tcl15 0 0 1 1 0 0 1 1 0 0 1 1 selects count clock of 8-bit timer register 2 falling edge of ti2 rising edge of ti2 f x /2 2 (2.5 mhz) f x /2 3 (1.25 mhz) f x /2 4 (625 khz) f x /2 5 (313 khz) f x /2 6 (156 khz) f x /2 7 (78.1 khz) f x /2 8 (39.1 khz) f x /2 9 (19.6 khz) f x /2 10 (9.8 khz) f x /2 12 (2.4 khz) setting prohibited tcl14 0 1 0 1 0 1 0 1 0 1 0 1 others
125 chapter 6 applications of 8-bit timer/event counter figure 6-2. format of timer cock select register 50 ( m pd780024, 780024y, 780034, 780034y subseries) tcl502 tcl501 tcl500 selects count clock 0 0 0 falling edge of ti50 0 0 1 rising edge of ti50 010f x (8.38 mhz) 011f x /2 2 (2.09 mhz) 100f x /2 4 (523 khz) 101f x /2 6 (131 khz) 110f x /2 8 (32.7 khz) 111f x /2 10 (8.18 khz) cautions 1. before writing new data to tcl50, stop the timer operation. 2. be sure to clear bits 3 through 7 to 0. remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 8.38 mhz figure 6-3. format of timer cock select register 50 ( m pd780924, 780964 subseries) tcl502 tcl501 tcl500 selects count clock 0 0 0 falling edge of ti50 0 0 1 rising edge of ti50 010f x /2 (4.19 mhz) 011f x /2 3 (1.05 mhz) 100f x /2 5 (262 khz) 101f x /2 7 (65.5 khz) 110f x /2 9 (16.4 khz) 111f x /2 11 (4.09 khz) cautions 1. before writing new data to tcl50, stop the timer operation. 2. be sure to clear bits 3 through 7 to 0. remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 8.38 mhz 7 0 6 0 5 0 4 0 3 0 2 tcl502 1 tcl501 0 tcl500 symbol tcl50 address ff69h at reset 00h r/w r/w 7 0 6 0 5 0 4 0 3 0 2 tcl502 1 tcl501 0 tcl500 symbol tcl50 address ff71h at reset 00h r/w r/w
126 chapter 6 applications of 8-bit timer/event counter figure 6-4. format of timer cock select register 51 ( m pd780024, 780024y, 780034, 780034y subseries) tcl512 tcl511 tcl510 selects count clock 0 0 0 falling edge of ti51 0 0 1 rising edge of ti51 010f x /2 (4.19 mhz) 011f x /2 3 (1.04 mhz) 100f x /2 5 (261 khz) 101f x /2 7 (65.4 khz) 110f x /2 9 (16.3 khz) 111f x /2 11 (4.09 khz) cautions 1. before writing new data to tcl51, stop the timer operation. 2. be sure to clear bits 3 through 7 to 0. remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 8.38 mhz figure 6-5. format of timer cock select register 51 ( m pd780924, 780964 subseries) tcl512 tcl511 tcl510 selects count clock 0 0 0 falling edge of ti51 0 0 1 rising edge of t5i1 010f x (8.38 mhz) 011f x /2 (4.19 mhz) 100f x /2 2 (2.1 mhz) 101f x /2 3 (1.05 mhz) 110f x /2 4 (524 khz) 111f x /2 5 (262 khz) cautions 1. before writing new data to tcl51, stop the timer operation. 2. be sure to clear bits 3 through 7 to 0. remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 8.38 mhz 7 0 6 0 5 0 4 0 3 0 2 tcl512 1 tcl511 0 tcl510 symbol tcl51 address ff71h at reset 00h r/w r/w 7 0 6 0 5 0 4 0 3 0 2 tcl512 1 tcl511 0 tcl510 symbol tcl51 address ff79h at reset 00h r/w r/w
127 chapter 6 applications of 8-bit timer/event counter figure 6-6. format of timer cock select register 52 ( m pd780924, 780964 subseries) tcl522 tcl521 tcl520 selects count clock 0 0 0 falling edge of ti52 0 0 1 rising edge of ti52 010f x /2 4 (524 khz) 011f x /2 5 (262 khz) 100f x /2 6 (131 khz) 101f x /2 7 (65.5 khz) 110f x /2 8 (32.7 khz) 111f x /2 9 (16.4 khz) cautions 1. before writing new data to tcl52, stop the timer operation. 2. be sure to clear bits 3 through 7 to 0. remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 8.38 mhz figure 6-7. format of 8-bit timer mode control register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) cautions 1. before changing the operation mode, stop the timer operation. 2. when using the 8-bit timer register as a 16-bit timer register, enable or stop the operation by using tce1. 765432 symbol 10 tce1 controls operation of 8-bit timer register 1 ff49h tce1 tmc1 tce2 0 tmc12 0 0 0 0 address at reset r/w 00h r/w 0 stops operation (clears tm1 to 0) 1 enables operation tce2 controls operation of 8-bit timer register 2 0 stops operation (clears tm2 to 0) 1 enables operation tmc12 selects operation mode 0 8-bit timer register 2 channel mode (tm1, tm2) 1 16-bit timer register 1 channel mode (tms) 7 0 6 0 5 0 4 0 3 0 2 tcl522 1 tcl521 0 tcl520 symbol tcl52 address ff79h at reset 00h r/w r/w
128 chapter 6 applications of 8-bit timer/event counter figure 6-8. format of 8-bit timer mode control register 5n ( m pd780024, 780024y, 780034, 780034y subseries) toe5n controls timer output 0 disables output (port mode) 1 enables output tmc5n1 other than pwm mode pwm mode (tmc5n6 = 0) (tmc5n6 = 1) controls timer f/f selects active level 0 disables reverse operation active high 1 enables reverse operation active low lvs5n lvr5n sets status of timer output f/f 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited tmc5n4 selects single mode/cascade connection mode 0 single mode (used with the lowest timer) 1 cascade connection mode (connected to the lower timer) tmc5n6 selects operating mode of tm5n 0 clear & start mode on coincidence of tm50 and cr50 1 pwm (free running) mode tce5n controls count operation of tm5n 0 clears count to 0 and disables counting (prescaler disabled) 1 starts count operation notes 1. address of tmc50 2. address of tmc51 remarks 1. pwm output becomes inactive level because tce5n = 0 in pwm mode. 2. lvs5n and lvr5n are always 0 when they are read after data has been set. 3. n = 0, 1 7 tce5n 6 tmc5n6 5 0 4 tmc5n4 3 lvs5n 2 lvr5n 1 tmc5n1 0 toe5n symbol tmc5n address ff70h note1 ff78h note2 at reset 00h r/w r/w
129 chapter 6 applications of 8-bit timer/event counter figure 6-9. format of 8-bit timer mode control register 50 ( m pd780924, 780964 subseries) toe50 controls timer output 0 disables output (port mode) 1 enables output tmc501 other than pwm mode pwm mode (tmc506 = 0) (tmc506 = 1) controls timer f/f selects active level 0 disables reverse operation active high 1 enables reverse operation active low lvs50 lvr50 sets status of timer output f/f 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited tmc506 selects operating mode of tm50 0 clear & start mode on coincidence of tm50 and cr50 1 pwm (free running) mode tce50 controls count operation of tm50 0 clears count to 0 and disables counting (prescaler disabled) 1 starts count operation remarks 1. pwm output becomes inactive level because tce50 = 0 in pwm mode. 2. lvs50 and lvr50 are always 0 when they are read after data has been set. 7 tce50 6 tmc506 5 0 4 0 3 lvs50 2 lvr50 1 tmc501 0 toe50 symbol tmc50 address ff68h at reset 04h r/w r/w
130 chapter 6 applications of 8-bit timer/event counter figure 6-10. format of 8-bit timer mode control register 51 ( m pd780924, 780964 subseries) toe51 controls timer output 0 disables output (port mode) 1 enables output tmc511 other than pwm mode pwm mode (tmc516 = 0) (tmc516 = 1) controls timer f/f selects active level 0 disables reverse operation active high 1 enables reverse operation active low lvs51 lvr51 sets status of timer output f/f 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited tmc514 selects single mode/cascade connection mode 0 single mode 1 cascade connection mode (connected to tm50) tmc516 selects operating mode of tm51 0 clear & start mode on coincidence of tm51 and cr51 1 pwm (free running) mode tce51 controls count operation of tm51 0 clears count to 0 and disables counting (prescaler disabled) 1 starts count operation remarks 1. pwm output becomes inactive level because tce51 = 0 in pwm mode. 2. lvs51 and lvr51 are always 0 when they are read after data has been set. 7 tce51 6 tmc516 5 0 4 tmc514 3 lvs51 2 lvr51 1 tmc511 0 toe51 symbol tmc51 address ff70h at reset 04h r/w r/w
131 chapter 6 applications of 8-bit timer/event counter figure 6-11. format of 8-bit timer mode control register 52 ( m pd780924, 780964 subseries) toe52 controls timer output 0 disables output (port mode) 1 enables output tmc521 other than pwm mode pwm mode (tmc526 = 0) (tmc526 = 1) controls timer f/f selects active level 0 disables reverse operation active high 1 enables reverse operation active low lvs52 lvr52 sets status of timer output f/f 0 0 not affected 0 1 resets timer output f/f (0) 1 0 sets timer output f/f (1) 1 1 setting prohibited tmc524 selects single mode/cascade connection mode 0 single mode 1 cascade connection mode (connected to tm51) tmc526 selects operating mode of tm52 0 clear & start mode on coincidence of tm52 and cr52 1 pwm (free running) mode tce52 controls count operation of tm52 0 clears count to 0 and disables counting (prescaler disabled) 1 starts count operation remarks 1. pwm output becomes inactive level because tce52 = 0 in pwm mode. 2. lvs52 and lvr52 are always 0 when they are read after data has been set. 7 tce52 6 tmc526 5 0 4 tmc524 3 lvs52 2 lvr52 1 tmc521 0 toe52 symbol tmc52 address ff78h at reset 04h r/w r/w
132 chapter 6 applications of 8-bit timer/event counter figure 6-12. format of 8-bit timer output control register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) cautions 1. before setting toc1, be sure to stop the timer operation. 2. lvs1, lvs2, lvr1, and lvr2 are always 0 when they are read. 765432 symbol 10 toe1 controls output of 8-bit timer/event counter 1 ff4fh toe1 toc1 toc11 lvs1 lvr1 toe2 toc15 lvr2 lvs2 address at reset r/w 00h r/w 0 disables output (port mode) 1 enables output toc11 controls timer output f/f of 8-bit timer/event counter 1 0 disables reverse operation 1 enables reverse operation lvs1 sets status of timer output f/f of 8-bit timer/ event counter 1 0 not affected 0 resets timer output f/f (to 0) lvr1 0 1 1 sets timer output f/f (to 1) setting prohibited 0 1 toe2 controls output of 8-bit timer/event counter 2 0 disables output (port mode) 1 enables output toc15 controls timer output f/f of 8-bit timer/event counter 2 0 disables reverse operation 1 enables reverse operation lvs2 sets status of timer output f/f of 8-bit timer/ event counter 2 0 not affected 0 resets timer output f/f (to 0) lvr2 0 1 1 sets timer output f/f (to 1) 1 setting prohibited 0 1 1
133 chapter 6 applications of 8-bit timer/event counter figure 6-13. format of port mode register 3 ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001) caution when using p31/to1, p32/to2 pins as timer outputs, set both pm31, pm32 and p31, p32 output latches to 0. figure 6-14. format of port mode register 7 ( m pd780024, 780024y, 780034, 780034y subseries) 765432 symbol 10 pm3n selects input/output mode of p3n pin (n = 0-7) ff23h pm30 pm3 pm31 pm33 pm32 pm34 pm35 pm36 pm37 address at reset r/w ffh r/w 0 output mode (output buffer on) 1 input mode (output buffer off) 765432 symbol 10 pm7n selects input/output mode of p7n pin (n = 0-5) ff27h pm70 pm7 pm71 pm73 pm72 pm74 pm75 1 1 address at reset r/w ffh r/w 0 output mode (output buffer on) 1 input mode (output buffer off)
134 chapter 6 applications of 8-bit timer/event counter 6.1 setting of interval timer when using an 8-bit timer/event counter as an interval timer, set an operation mode by the 8-bit timer mode control register (tmc1) and interval time by the timer clock select register 1 (tcl1). after that, set the values of the compare registers (cr10 and cr20) from the setup time and count clock. the setup time is determined by using the following expression: setup time = (compare register value + 1) count clock cycle the setup time can be calculated in the same manner regardless of whether each 8-bit timer/event counter is used or two 8-bit timers/event counters are used as a 16-bit timer/event counter. the count clock when two 8-bit timers/ event counters are used as a 16-bit timer/event counter, however, is selected by the bits 0 through 3 (tcl10 through tcl13) of tcl1. examples of the modes of the 8-bit timers and 16-bit timer are described next. figure 6-15. count timing of 8-bit timers count clock tm1, tm2 inttm1, inttm2 to1 n? n? n 00 01 02 n? n? n
135 chapter 6 applications of 8-bit timer/event counter 6.1.1 setting of 8-bit timers in this example, 8-bit timer 2 of the m pd78014 subseries is used to set two types of interval times: 500 m s and 100 ms. (a) to set interval of 500 m s <1> setting of tmc1 select the 8-bit timer register 2 channel mode and enables the operation of the 8-bit timer 2. <2> setting of tcl1 select f x /2 5 that allows setting of 500 m s or more and has the highest resolution. <3> setting of cr20 500 m s = (n + 1) n = 500 m s 8.38 mhz/2 5 C 1 = 130 (1) program list tcl1 = #10011001b ; selects f x /2 5 as count clock cr20 = #130 tmc1 = #00000010b (b) to set interval of 100 ms <1> setting of tmc1 select the 8-bit timer register 2 channel mode and enables the operation of the 8-bit timer 2. <2> setting of tcl1 select f x /2 12 that allows setting of 100 ms or more and has the highest resolution. <3> setting of cr20 100 ms = (n + 1) n = 100 ms 8.38 mhz/2 12 C 1 = 204 (1) program list tcl1 = #11111111b ; selects f x /2 12 as count clock cr20 = #204 tmc1 = #00000010b 1 8.38 mhz/2 5 ? ? 1 8.38 mhz/2 12 ? ?
136 chapter 6 applications of 8-bit timer/event counter 6.1.2 setting of 16-bit timer in this example, 8-bit timers 1 and 2 of the m pd78014 subseries are connected in cascade as a 16-bit timer to set two types of interval times: 500 ms and 10 s. (a) to set interval of 500 ms <1> setting of tmc1 select the 16-bit timer register 1 channel mode and enables the operation of the 8-bit timers 1 and 2. <2> setting of tcl1 select f x /2 6 that allows setting of 500 ms or more and has the highest resolution. <3> setting of cr10 and cr20 500 ms = n = 500 ms 8.38 mhz/2 6 C 1 = 65468 = ff6ch cr10 = 6ch, cr20 = ffh (1) program list tcl1 = #00001010b cr10 = #06ch ; sets 65468 to cr10 and cr20 cr20 = #0ffh ; cr10 = 6ch, cr20 = ffh tmc1 = #00000111b (b) to set interval of 10 s <1> setting of tmc1 select the 16-bit timer register 1 channel mode and enable the operation of the 8-bit timers 1 and 2. <2> setting of tcl1 select f x /2 12 that allows setting of 10 s or more and has the highest resolution. <3> setting of cr10 and cr20 10 s = n = 10 s 8.38 mhz/2 12 C 1 = 20458 = 4feah cr10 = eah, cr20 = 4fh (1) program list tcl1 = #00001111b cr10 = #0eah ; sets 20458 to cr10 and cr20 cr20 = #4fh ; cr10 = eah, cr20 = 4fh tmc1 = #00000111b n + 1 8.38 mhz/2 6 ? ? n + 1 8.38 mhz/2 12 ? ?
137 chapter 6 applications of 8-bit timer/event counter 6.2 musical scale generation this section shows an example of a program that uses the square wave output (p31/to1) of an 8-bit timer/event counter of the m pd78014 subseries and generates a musical scale by supplying pulses to an external buzzer. figure 6-16. musical scale generation circuit the output frequency of the p31/to1 pin is set by the count clock and a compare register. in this example, the central frequency of the musical scale is set to a range of 523 to 1046 hz. therefore, f x /2 6 is selected as the count clock. table 6-1 shows the musical scale, the set value of the compare register, and frequency of the output pulse. because one cycle of the timer output is created when the value of the timer coincides with the value of the compare register two times, the interval time is set as half a cycle time. figure 6-17. timer output and interval interval cr10 coincidence interval timer output cycle pd78014 m v dd p31/to1
138 chapter 6 applications of 8-bit timer/event counter as for the time length of a sound, the output time is determined by setting an interval time with 8-bit timer/event counter 2 and by counting the number of times the interrupt generated by the timer/event counter. in this example, 8-bit timer/event counter 2 is set to 20 ms. table 6-1. musical scale and frequency musical scale musical scale frequency hz compare register value output frequency hz do 523.25 124 524.3 re 587.33 111 585.1 mi 659.25 98 662.0 fa 698.46 93 697.2 so 783.98 83 780.2 la 880.00 73 885.6 tee 987.77 65 993.0 do 1046.5 62 1040 the format of the data table for this program is shown below. table: db musical scale data 1, sound length data 1 db musical scale data 2, sound length data 2 db musical scale data n, sound length data n db 0, 0 the musical scale data is set to 0 for rest, and the sound length data is set to 0 for the end of data. example number of counts of 8-bit timer/event counter to output sound for 1 second number of counts = 1 s/20 ms = 50 (50 is set as number of counts) this program sequentially outputs do, re, mi, and so on, for 1 second each. . . . . . .
139 chapter 6 applications of 8-bit timer/event counter (1) description of package mldy: subroutine name of musical scale generation program bank 0: a, b, hl name usage attribute bytes point stores pointer value of table data saddr 1 lng counts sound length data 1 level 3 bytes ? 8-bit timer/event counters 1 and 2 ? p31/to1 ? sets by subroutine mldy ? enables interrupt ? call subroutine mldy (2) example of use extrn mldy call !mldy ei . . .
140 chapter 6 applications of 8-bit timer/event counter (3) spd chart (4) program list public mldy vetm2 cseg at 18h dw inttm2 ml_dat dseg saddr point: ds 1 lng: ds 1 ;************************************************* ;* musical scale generation initialize ;************************************************* ml_seg cseg mldy: clr pm3.1 point=#0 lgn=#1 osms=#00000001b toc1=#00000011b tcl1=#11101010b cr20=#163 tmc1=#00000010b clr1 tmmk2 ret $eject mldy sets p31/to1 in output mode clears pointer (point) of reference table to 0 sets initial data 1 as sound length data (lng) sets 8-bit timer/event counter 1 in output mode sets 8-bit timer/event counter 2 to 20 ms enables 8-bit timer 2 interrupt inttm2 selects register bank 0 decrements sound length data (lng) if: end of output time references sound data indicated by pointer if: sound data 1 mute data sets sound data to compare register of timer 1 disables to1 output of timer 1 references sound length data if: sound length data 1 musical scale generation end data sets sound length data disables timer 2 interrupt stops timer 2 operation then else else then then ; sets vector address of 8-bit timer/event counter ; pointer for table data ; sound length data ; sets p3.1 in output mode ; initial setting of pointer ; does not use divider circuit ; sets to1 output mode ; sets timer 2 to 20 ms ; enables timer 2 operation ; enables timer 2 interrupt
141 chapter 6 applications of 8-bit timer/event counter ;*********************************************** ; sets musical scale generation data ;*********************************************** tm2_seg cseg inttm2: sel rb0 lng C C if(lng==#0) b=point (a) hl=#table a=[hl+b] if(a!=#0) clr1 tce1 cr10=a set1 toe1 set1 tce1 else clr1 toe1 endif b++ a=[hl+b] if(a!=#0) lng=a b++ point=b (a) else set1 tmmk2 clr1 tce2 endif endif reti ;*********************************************** ; musical scale data table ;*********************************************** table: db 124,50 db 111,50 db 98,50 db 93,50 db 83,50 db 73,50 db 65,50 db 62,50 db 00,00 ; sets table first address ; sets sound data ; increments pointer ; loads sound length data ; sound output in progress? ; sets sound length data ; disables timer 2 interrupt ; stops timer 2 operation ;do ;re ;mi ;fa ;so ;la ; tee ;do ; end
142 chapter 6 applications of 8-bit timer/event counter [memo]
143 chapter 7 applications of watch timer chapter 7 applications of watch timer the watch timer of the 78k/0 series has a watch timer function that causes the timer to overflow every 0.5 second by using the main system clock or subsystem clock as the clock source, and an interval timer function that allows you to set six types of reference times. these two functions can be simultaneously used. the watch timer is set by using the following registers. ? timer clock select register 2 (tcl2) : m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries ? watch timer mode control register (tmc2) : m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries ? watch timer mode control register(wtm) : m pd780024, 780024y, 780034, 780034y subseries caution the format of the registers provided on the m pd780024, 780024y, 780034, and 780034y subseries differs from the format of the registers used in the program examples in this chapter. when using a program example in this chapter with any of the m pd780024, 780024y, 780034, and 780034ysubseries, change the setting of the registers according to the registers of the microcontroller used.
144 chapter 7 applications of watch timer figure 7-1. format of timer clock select register 2 ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries) caution before writing new data to tcl2, stop the timer operation once. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. : dont care 4. ( ) : at f x = 10.0 mhz or f xt = 32.768 khz 7 tcl27 6 tcl26 5 tcl25 4 tcl24 3 0 2 tcl22 1 tcl21 0 tcl20 symbol tcl2 address ff42h at reset 00h r/w r/w tcl22 0 0 0 0 1 1 1 1 tcl21 0 0 1 1 0 0 1 1 tcl20 0 1 0 1 0 1 0 1 selects count clock of watchdog timer f x /2 4 (625 khz) f x /2 5 (313 khz) f x /2 6 (156 khz) f x /2 7 (78.1 khz) f x /2 8 (39.1 khz) f x /2 9 (19.5 khz) f x /2 10 (9.8 khz) f x /2 12 (2.4 khz) tcl24 0 1 selects count clock of watch timer f x /2 8 (39.1 khz) f xt (32.768 khz) tcl27 0 1 1 1 1 tcl26 0 0 1 1 tcl25 0 1 0 1 selects frequency of buzzer output disables buzzer output f x /2 10 (9.8 khz) f x /2 11 (4.9 khz) f x /2 12 (2.4 khz) setting prohibited
145 chapter 7 applications of watch timer figure 7-2. format of watch timer mode control register ( m pd78002, 78002y, 78014, 78014y, 78018f, 78018fy, 78014h subseries) 765432 symbol 10 tmc23 selects set time of watch flag ff4ah tmc20 tmc2 tmc21 tmc23 tmc22 tmc24 tmc25 tmc26 0 address at reset r/w 00h r/w tmc20 0 2 14 /f w (0.5s) 0 1 2 13 /f w (0.25s) 0 2 5 /f w (977 s) 1 1 2 4 /f w (488 s) m m tmc21 controls operation of prescaler 0 clears after operation stopped 1 enables operation tmc22 controls operation of 5-bit counter 0 clears after operation stopped 1 enables operation tmc26 selects interval time of prescaler 0 0 tmc25 0 0 0 2 6 /f w (1.95 ms) 0 2 7 /f w (3.91 ms) 1 1 tmc24 0 1 0 1 1 2 8 /f w (7.81 ms) 1 2 9 /f w (15.6 ms) 0 0 others setting prohibited 0 1 2 4 /f w (488 s) m 2 5 /f w (977 s) m caution do not often clear the prescaler when the watch timer is used. remarks 1. f w : watch timer clock frequency (f x /2 8 or f xt ) 2. ( ): at f w = 32.768 khz
146 chapter 7 applications of watch timer figure 7-3. format of watch timer mode control register ( m pd780024, 780024y, 780034, 780034y subseries) wtm0 enables watch timer operation 0 stops operation (clears both prescaler and timer) 1 enables operation wtm1 controls 5-bit counter operation 0 stops and clears 1 starts wtm6 wtm5 wtm4 selects interval timer of prescaler 0002 4 /f w (488 m s) 0012 5 /f w (977 m s) 0102 6 /f w (1.95 ms) 0112 7 /f w (3.91 ms) 1002 8 /f w (7.81 ms) 1012 9 /f w (15.6 ms) others setting prohibited wtm7 selects count clock of watch timer 0f x /2 7 (65.4 khz) 1f xt (32.768 khz) remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. ( ): f x = 8.38 mhz or f w = 32.768 khz 7 wtm7 6 wtm6 5 wtm5 4 wtm4 3 0 2 0 1 wtm1 0 wtm0 symbol wtm address ff41h at reset 00h r/w r/w
147 chapter 7 applications of watch timer 7.1 watch and led display program as an example of using the watch timer of the m pd78014 subseries, this section introduces a program that counts time by using an 0.5 second overflow and dynamically displays led at intervals of 1.95 ms. to count time, an overflow flag is tested each time a subroutine is called. when the flag is set, time is counted up in seconds. because an overflow occurs every 0.5 second, it takes 1 minute to count 120 times. the overflow flag is tested at intervals of 1.95 ms so that the flag is tested without fail. the watch of this program is 24-hour watch. the high-order and low-order digits of minute and hour data are stored in separate areas of memory. figure 7-4. concept of watch data second data minute data hour data 0-120 low-order digit 0-9 high-order digit 0-5 low-order digit 0-9 high-order digit 0-2
148 chapter 7 applications of watch timer as led dynamic display, four digits are displayed with the display digit changed at intervals of 1.95 ms. in this example, the high-order 4 bits of p3 are used as a digit signal, and p5 that can directly drive an led is selected as a segment signal. the digit of an led specified by a display digit area (digct) in an led display area is displayed. to change the digit signal, the segment signal is turned off so that the adjacent digits are not displayed. figure 7-5. led display timing figure 7-6. circuit example of watch timer p34 p35 p36 p37 port 5 digit 012301230123 segment signal off pd78014 m p37 p36 p35 p34 p50 ? p57 7-segment led 4
149 chapter 7 applications of watch timer (1) description of package secd : second data storage area mindp : minute data storage area hourdp : hour data storage area leddp : led display area bank 0: ax, b, hl name usage attribute bytes mindp stores minute data saddrp 2 hourdp stores hour data secd stores second data 1 digct stores led display digit data leddp led display data 4 ? watch timer ? p34-37 ? p5 ? 0.5-second watch operation at 1.95 ms interval tmc2 = #00100110b ? enables watch timer interrupt tmmk3 = 0 started by the interval timer interrupt request of the watch timer. (2) example of use extrn mindp, hourdp, secd, leddp tmc2 = #00100110b ; 0.5-second watch operation at 1.95 ms interval clr1 tmmk3 ; enables watch timer interrupt ei
150 chapter 7 applications of watch timer (3) spd chart inttm3 selects register bank 0 watch count time led display leddsp leddsp turns off segment signal if: digit counter (digct) = 0 initial setting of digit signal shifts digit signal i bit higher then else outputs segment signal of digit indicated by digit counter increments digit counter time if: sets watch timer interrupt request flag increments second counter if: second counter = 120 sets second counter to 0 increments minute (low) counter if: minute (low) counter = 10 then then then clears minute (low) counter to 0 increments minute (high) counter if: minute (high) counter = 6 then clears minute (high) counter to 0 increments hour (low) counter if: hour data 1 0204h if: hour (low) counter = 10 clears hour (low) counter to 0 increments hour (high) counter clears hour counter to 0 then then else
151 chapter 7 applications of watch timer (4) program list public hourdp,mindp,secd,leddp wt_datp dseg saddrp mindp: ds 2 hourdp: ds 2 secd: ds 1 digct: ds 1 leddp: ds 4 vetm3 cseg at 1eh dw inttm3 ;*************************************** ;* interval interrupt processing ;*************************************** tm3_seg cseg inttm3: sel rb0 call !time call !leddpsp reti ; minute data storage area ; hour data storage area ; second data storage area ; led display digit area ; led display area ; sets vector address of watch timer
152 chapter 7 applications of watch timer ;************************************ ; led display ;************************************ leddpsp: p5=#0ffh digct&=#00000011b if(digct==#0) a=p3 a&=#00001111b a|=#00010000b p3=a else a=p3 a&=#11110000b x=a a=p3 a+=x p3=a endif b=digct (a) hl=#leddp b=[hl+b] (a) hl=#segdt p5=[hl+b] (a) digct++ ret segdt: db 11000000b db 11111001b db 10100100b db 10110000b db 10011001b db 10010010b db 10000010b db 11111000b db 10000000b db 10010000b db 10001000b db 10000011b db 11000110b db 10100001b db 10000110b db 10001110b $eject ; turns off segment output ; adjusts digit counter (0-3) ; initial setting of digit signal (high-order 4 bits) ; shifts high-order 4 bits ; sets address of display data ; display area first address ; sets display data ; conversion to segment data ; outputs segment signal ;0 ;1 ;2 ;3 ;4 ;5 ;6 ;7 ;8 ;9 ;a ;b ;c ;d ;e ;f
153 chapter 7 applications of watch timer ;******************************** ;* watch count up ;******************************** time: if_bit(wtif) clr1 wtif secd++ if(secd==#120) secd=#0 (mindp+0)++ if((mindp+0)==#10) (mindp+0)=#0 (mindp+1)++ if(mindp+1==#6) (mindp+1)=#0 (hourdp+0)++ if(hourdp!=#0204h) (ax) if((hourdp+0)==#10) (hourdp+0)=#0 (hourdp+1)++ endif else hourdp=#0000h endif endif endif endif endif ret ; 0.5 second test ; 120 = 60 seconds/0.5 ; increments minute (low) ; carry occurs ; increments minute (high) ; carry occurs ; hour data 24? ; carry occurs
154 chapter 7 applications of watch timer [memo]
155 chapter 8 applications of serial interface chapter 8 applications of serial interface the 78k/0 series is provided with the serial interface shown in table 8-1. table 8-1. serial interface channel of each subseries channel 0 channel 1 sio3 uart0 3-wire 2-wire sbi i 2 c bus 3-wire 3-wire 3-wire async. with serial automatic interface transmit/ receive function m pd78002 m pd78002y m pd78014 m pd78014y m pd78018f m pd78018fy m pd780001 m pd780024 m pd780024y m pd780034 m pd780034y m pd78014h m pd780924 m pd780964 remark : function provided, : function not provided the functions and operations of the serial interface are specified by using the following registers: table 8-2. registers of serial interface serial interface register used remark this chapter describes the register formats and application examples of serial interface channels 0, 1, and 2. for details of the register formats of serial interface sio3 and uart0, refer to the users manual of each subseries. configuration of serial interface subseries channel 0 ? timer clock select register (tcl3) ? serial operating mode register 0 (csim0) ? serial bus interface control register (sbic) ? interrupt timing specification register (sint) channel 1 ? timer clock select register (tcl3) ? serial operating mode register 1 (csim1) ? automatic data transmit/receive control register (adtc) ? automatic data transmit/receive interval specification register (adti)
156 chapter 8 applications of serial interface figure 8-1. format of timer clock select register 3 ( m pd78002 subseries) note can be set only when the main system clock frequency is 4.19 mhz or less. cautions 1. be sure to set bit 7 to 1, and bits 6 through 4 to 0. 2. before writing new data to tcl3, stop serial transfer once. remarks 1. f x : main system clock oscillation frequency 2. ( ) : at f x = 10.0 mhz 7 1 6 0 5 0 4 0 3 tcl33 2 tcl32 1 tcl31 0 tcl30 symbol tcl3 address ff43h at reset 88h r/w r/w tcl33 0 0 1 1 1 1 1 1 tcl32 1 1 0 0 0 0 1 1 tcl31 1 1 0 0 1 1 0 0 selects serial clock of serial interface channel 0 f x /2 2 note f x /2 3 (1.25 mhz) f x /2 4 (625 khz) f x /2 5 (313 khz) f x /2 6 (156 khz) f x /2 7 (78.1 khz) f x /2 8 (39.1 khz) f x /2 9 (19.5 khz) setting prohibited tcl30 0 1 0 1 0 1 0 1 others
157 chapter 8 applications of serial interface figure 8-2. format of timer clock select register 3 ( m pd78002y subseries) tcl33 tcl32 tcl31 tcl30 selects serial clock of serial interface channel 0 0110f x /2 6 (156 khz) f x /2 2 note 0111f x /2 7 (78.1 khz) f x /2 3 (1.25 mhz) 1000f x /2 8 (39.1 khz) f x /2 4 (625 khz) 1001f x /2 9 (19.5 khz) f x /2 5 (313 khz) 1010f x /2 10 (9.8 khz) f x /2 6 (156 khz) 1011f x /2 11 (4.9 khz) f x /2 7 (78.1 khz) 1100f x /2 12 (2.4 khz) f x /2 8 (39.1 khz) 1101f x /2 13 (1.2 khz) f x /2 9 (19.5 khz) others setting prohibited note can be set only when the main system clock frequency is 4.19 mhz or less. cautions 1. be sure to set bit 7 to 1, and bits 6 through 4 to 0. 2. before writing new data to tcl3, stop serial transfer once. remarks 1. f x : main system clock oscillation frequency 2. ( ) : at f x = 10.0 mhz serial clock in 3-wire serial i/o/sbi/2-wire serial i/o mode serial clock in i 2 c bus mode 765432 symbol 10 ff43h tcl30 tcl3 tcl31 tcl33 tcl32 0 0 0 1 address at reset r/w 88h r/w
158 chapter 8 applications of serial interface figure 8-3. format of timer clock select register 3 ( m pd78014, 78018f, 78014h subseries) tcl33 tcl32 tcl31 tcl30 selects serial clock of serial interface channel 0 0 110f x /2 2 note 0 111f x /2 3 (1.25 mhz) 1 000f x /2 4 (625 khz) 1 001f x /2 5 (313 khz) 1 010f x /2 6 (156 khz) 1 011f x /2 7 (78.1 khz) 1 100f x /2 8 (39.1 khz) 1 101f x /2 9 (19.5 khz) others setting prohibited tcl37 tcl36 tcl35 tcl34 selects serial clock of serial interface channel 1 0 110f x /2 2 note 0 111f x /2 3 (1.25 mhz) 1 000f x /2 4 (625 khz) 1 001f x /2 5 (313 khz) 1 010f x /2 6 (156 khz) 1 011f x /2 7 (78.1 khz) 1 100f x /2 8 (39.1 khz) 1 101f x /2 9 (19.5 khz) others setting prohibited note can be set only when the main system clock frequency is 4.19 mhz or less. caution before writing new data to tcl3, stop serial transfer once. remarks 1. f x : main system clock oscillation frequency 2. ( ) : at f x = 10.0 mhz 765432 symbol 10 ff43h tcl30 tcl3 tcl31 tcl33 tcl32 tcl34 tcl35 tcl36 tcl37 address at reset r/w 88h r/w
159 chapter 8 applications of serial interface figure 8-4. format of timer clock select register 3 ( m pd78014y, 78018fy subseries) tcl33 tcl32 tcl31 tcl30 selects serial clock of serial interface channel 0 0110f x /2 6 (156 khz) f x /2 2 note 2 0111f x /2 7 (78.1 khz) f x /2 3 (1.25 mhz) 1000f x /2 8 (39.1 khz) f x /2 4 (625 khz) 1001f x /2 9 (19.5 khz) f x /2 5 (313 khz) 1010f x /2 10 (9.8 khz) f x /2 6 (156 khz) 1011f x /2 11 (4.9 khz) f x /2 7 (78.1 khz) 1100f x /2 12 (2.4 khz) f x /2 8 (39.1 khz) 1101f x /2 13 (1.2 khz) f x /2 9 (19.5 khz) others setting prohibited tcl37 tcl36 tcl35 tcl34 selects serial clock of serial interface channel 1 0110f x /2 2 note 2 0111f x /2 3 (1.25 mhz) 1000f x /2 4 (625 khz) 1001f x /2 5 (313 khz) 1010f x /2 6 (156 khz) 1011f x /2 7 (78.1 khz) 1100f x /2 8 (39.1 khz) 1101f x /2 9 (19.5 khz) others setting prohibited notes 1. sbi mode is not provided for the m pd78018fy subseries. 2. can be set only when the main system clock frequency is 4.19 mhz or less. caution before writing new data to tcl3, stop serial transfer once. remarks 1. f x : main system clock oscillation frequency 2. ( ) : at f x = 10.0 mhz serial clock in 3-wire serial i/o/sbi/ 2-wire serial i/o mode note 1 serial clock in i 2 c bus mode 765432 symbol 10 ff43h tcl30 tcl3 tcl31 tcl33 tcl32 address at reset r/w 88h r/w tcl34 tcl35 tcl37 tcl36
160 chapter 8 applications of serial interface figure 8-5. format of timer clock select register 3 ( m pd780001) note can be set only when the main system clock frequency is 4.19 mhz or less. caution before writing new data to tcl3, stop serial transfer once. remarks 1. f x : main system clock oscillation frequency 2. ( ) : at f x = 10.0 mhz tcl37 tcl36 tcl35 tcl34 1 0 0 0 tcl3 76543210 symbol address at reset r/w ff43h 88h r/w tcl37 tcl36 0 0 1 1 1 1 0 0 tcl35 tcl34 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 0 1 0 0 1 selects serial clock of serial interface channel 1 f x /2 2 note f x /2 3 (1.25 mhz) f x /2 4 (625 khz) f x /2 5 (313 khz) f x /2 6 (156 khz) f x /2 7 (78.1 khz) f x /2 8 (39.1 khz) f x /2 9 (19.5 khz) setting prohibited others
161 chapter 8 applications of serial interface figure 8-6. format of serial operating mode register 0 ( m pd78002, 78014, 78018f, 78014h subseries) (1/2) r/w csim csim selects clock of serial interface channel 0 01 00 0 clock externally input to sck0 pin 1 0 output of 8-bit timer register 2 (tm2) 1 1 clock specified by bits 0 through 3 of timer clock select register 3 (tcl3) r/w csim csim csim pm25 p25 pm26 p26 pm27 p27 operating mode first bit function of function of function of 04 03 02 si0/sb0/p25 pin so0/sb1/p26 pin sck0/p27 pin 0 01 0 0 0 1 3-wire serial msb si0 note 2 so0 sck0 1 i/o mode lsb (input) (cmos output) (cmos i/o) 10 0 note 3 note 3 0 0 0 1 sbi mode msb p25 sb1 sck0 (cmos i/o) (n-ch open drain (cmos i/o) i/o) 100 note 3 note 3 0 1 sb0 p26 (n-ch open drain (cmos i/o) i/o) 11 0 note 3 note 3 0 0 0 1 2-wire serial msb p25 sb1 sck0 i/o mode (cmos i/o) (n-ch open drain (n-ch open drain i/o) i/o) 100 note 3 note 3 0 1 sb0 p26 (n-ch open drain (cmos i/o) i/o) r/w wup controls wake-up function note 4 0 generates interrupt request signal in all modes each time serial transfer is executed 1 generates interrupt request signal when address received after bus has been released (when cmdd = reld = 1) coincides with data of slave address register in sbi mode notes 1. bit 6 (coi) is a read-only bit. 2. when only the transmission function is used, this pin can be used as p25 (cmos i/o). 3. these pins can be used as port pins. 4. when using the wake-up function (wup = 1), clear bit 5 (sic) of the interrupt timing specification register (sint) to 0. caution do not change the operating mode (3-wire serial i/o/2-wire serial i/o/sbi) while the operation of the serial interface channel 0 is enabled. to change the operating mode, stop the serial operation. remark : dont care pm : port mode register p : output latch of port 7 csie 0 6 coi 5 wup 4 csim 04 3 csim 03 2 csim 02 1 csim 01 0 csim 00 csim0 symbol ff60h address at reset r/w 00h r/w note 1
162 chapter 8 applications of serial interface figure 8-6. format of serial operating mode register 0 ( m pd78002, 78014, 78018f, 78014h subseries) (2/2) r coi slave address comparison result flag note 0 data of slave address register does not coincide with data of serial i/o shift register 1 data of slave address register coincides with data of serial i/o shift register r/w csie0 controls operation of serial interface channel 0 0 stops operation 1 enables operation note coi is 0 when csie0 = 0. caution do not change the operating mode (3-wire serial i/o/2-wire serial i/o/sbi) while the operation of the serial interface channel 0 is enabled. to change the operating mode, stop the serial operation.
163 chapter 8 applications of serial interface figure 8-7. format of serial operating mode register 0 ( m pd78002y, 78014y subseries) (1/2) r/w csim csim selects clock of serial interface channel 0 01 00 0 clock externally input to sck0/scl pin 1 0 output of 8-bit timer register 2 (tm2) note 2 1 1 clock specified by bits 0 through 3 of timer clock select register 3 (tcl3) r/w csim csim csim pm25 p25 pm26 p26 pm27 p27 operating mode first bit function of function of function of 04 03 02 si0/sb0/sda0/p25 pin so0/sb1/sda1/p26 pin sck0/scl/p27 pin 0 01 0 0 0 1 3-wire serial msb si0 note 3 so0 sck0 1 i/o mode lsb (input) (cmos output) (cmos i/o) 100 note 4 note 4 0 0 0 1 sbi mode msb p25 sb1 sck0 (cmos i/o) (n-ch open drain (cmos i/o) i/o) 100 note 4 note 4 0 1 sb0 p26 (n-ch open drain (cmos i/o) i/o) 110 note 4 note 4 0 0 0 1 2-wire serial msb p25 sb1 sck0/scl i/o mode or (cmos i/o) (n-ch open drain (n-ch open drain i2c bus mode i/o) i/o) 100 note 4 note 4 0 1 sb0/sda0 p26 (n-ch open drain (cmos i/o) i/o) r/w wup controls wake-up function note 5 0 generates interrupt request signal in all modes each time serial transfer is executed 1 generates interrupt request signal when address received after bus release (when cmdd = reld = 1 in sbi mode, cmdd = 1 in i 2 c bus mode) coincides with data of slave address register in sbi or i 2 c mode notes 1. bit 6 (coi) is a read-only bit. 2. in the i 2 c bus mode, the clock frequency is 1/16 of the clock frequency output by to2 3. when only the transmission function is used, this pin can be used as p25 (cmos i/o). 4. these pins can be used as port pins. 5. when using the wake-up function (wup = 1), clear bit 5 (sic) of the interrupt timing specification register (sint) to 0. while wup = 1, do not execute an instruction that writes data to the i/o shift register 0 (sio0). caution do not change the operating mode (3-wire serial i/o/sbi/2-wire serial i/o/i 2 c bus) while the operation of the serial interface channel 0 is enabled. to change the operating mode, stop the serial operation. remark : dont care pm : port mode register p : output latch of port 7 csie 0 6 coi 5 wup 4 csim 04 3 csim 03 2 csim 02 1 csim 01 0 csim 00 csim0 symbol ff60h address at reset r/w 00h r/w note 1
164 chapter 8 applications of serial interface figure 8-7. format of serial operating mode register 0 ( m pd78002y, 780014y subseries) (2/2) r coi slave address comparison result flag note 0 data of slave address register does not coincide with data of serial i/o shift register 1 data of slave address register coincides with data of serial i/o shift register r/w csie0 controls operation of serial interface channel 0 0 stops operation 1 enables operation note coi is 0 when csie0 = 0. caution do not change the operating mode (3-wire serial i/o/sbi/2-wire serial i/o/i 2 c bus) while the operation of the serial interface channel 0 is enabled. to change the operating mode, stop the serial operation.
165 chapter 8 applications of serial interface figure 8-8. format of serial operating mode register 0 ( m pd78018fy subseries) (1/2) r/w csim csim selects clock of serial interface channel 0 01 00 0 clock externally input to sck0/scl pin 1 0 output of 8-bit timer register 2 (tm2) note 2 1 1 clock specified by bits 0 through 3 of timer clock select register 3 (tcl3) r/w csim csim csim pm25 p25 pm26 p26 pm27 p27 operating mode first bit function of function of function of 04 03 02 si0/sb0/sda0/p25 pin so0/sb1/sda1/p26 pin sck0/scl/p27 pin 0 01 0 0 0 1 3-wire serial msb si0 note 3 so0 sck0 1 i/o mode lsb (input) (cmos output) (cmos i/o) 11 0 note 4 note 4 0 0 0 1 2-wire serial msb p25 sb1 sck0/scl i/o mode or (cmos i/o) (n-ch open drain (n-ch open drain i 2 c bus mode i/o) i/o) 10 0 note 4 note 4 0 1 sb0/sda0 p26 (n-ch open drain (cmos i/o) i/o) r/w wup controls wake-up function note 5 0 generates interrupt request signal in all modes each time serial transfer is executed 1 generates interrupt request signal when address received after start condition has been detected (when cmdd = 1) coincides with data of slave address register in i 2 c mode notes 1. bit 6 (coi) is a read-only bit. 2. in the i 2 c bus mode, the clock frequency is 1/16 of the clock frequency output by to2 3. when only the transmission function is used, this pin can be used as p25 (cmos i/o). 4. these pins can be used as port pins. 5. when using the wake-up function (wup = 1), clear bit 5 (sic) of the interrupt timing specification register (sint) to 0. while wup = 1, do not execute an instruction that writes data to the i/o shift register 0 (sio0). caution do not change the operating mode (3-wire serial i/o/2-wire serial i/o/i 2 c bus) while the operation of the serial interface channel 0 is enabled. to change the operating mode, stop the serial operation. remark : dont care pm : port mode register p : output latch of port 7 csie 0 6 coi 5 wup 4 csim 04 3 csim 03 2 csim 02 1 csim 01 0 csim 00 csim0 symbol ff60h address at reset r/w 00h r/w note 1
166 chapter 8 applications of serial interface figure 8-8. format of serial operating mode register 0 ( m pd78018fy subseries) (2/2) r coi slave address comparison result flag note 0 data of slave address register does not coincide with data of serial i/o shift register 1 data of slave address register coincides with data of serial i/o shift register r/w csie0 controls operation of serial interface channel 0 0 stops operation 1 enables operation note coi is 0 when csie0 = 0. caution do not change the operating mode (3-wire serial i/o/2-wire serial i/o/i 2 c bus) while the operation of the serial interface channel 0 is enabled. to change the operating mode, stop the serial operation.
167 chapter 8 applications of serial interface figure 8-9. format of serial operating mode register 1 ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries only) csim csim selects clock of serial interface channel 1 11 10 0 clock externally input to sck1 pin note 1 1 0 output of 8-bit timer register 2 (tm2) 1 1 clock specified by bits 4 through 7 of timer clock select register 3 (tcl3) ate selects operation mode of serial interface channel 1 0 3-wire serial i/o mode 1 3-wire serial i/o mode with automatic transmit/receive function dir first bit function of si1 pin function of so1 pin 0 msb si1/p20 (input) so1 (cmos output) 1 lsb csie csim pm20 p20 pm21 p21 pm22 p22 operation of function of function of function of 111 shift register 1 si1/p20 pin so1/p21 pin sck1/p22 0 note 2 note 2 note 2 note 2 note 2 note 2 stops clear p20 p21 p22 operation (cmos i/o) (cmos i/o) (cmos i/o) 10 note 3 note 3 00 1 enables count operation si1 note 3 so1 sck1 1 operation (input) (cmos output) (input) 1 0 1 sck1 (cmos output) notes 1. clear bit 2 (strb) and bit 1 (busy1) of the automatic data transmit/receive control register (adtc) to 0, 0 when the external clock input is selected by clearing csim11 to 0. 2. these pins can be used as port pins. 3. when only transmission is executed, this pin can be used as p20 (cmos i/o). (set bit 7 (re) of the automatic data transmit/receive control register (adtc) to 0.) remark : dont care pm : port mode register p : output latch of port controls operation of counter of serial clock 7 csie 1 6 dir 5 ate 4 0 3 0 2 0 1 csim 11 0 csim 10 csim1 symbol ff68h address at reset r/w 00h r/w
168 chapter 8 applications of serial interface figure 8-10. format of serial operating mode register 1 ( m pd780001) csim csim selects clock of serial interface channel 1 11 10 0 clock externally input to sck1 pin note 1 1 0 output of 8-bit timer register 2 (tm2) 1 1 clock specified by bits 4 through 7 of timer clock select register 3 (tcl3) dir first bit function of si1 pin function of so1 pin 0 msb si1/p20 (input) so1 (cmos output) 1 lsb csie csim pm20 p20 pm21 p21 pm22 p22 operation of function of function of function of 111 shift register 1 si1/p20 pin so1/p21 pin sck1/p22 0 note 2 note 2 note 2 note 2 note 2 note 2 stops clear p20 p21 p22 operation (cmos i/o) (cmos i/o) (cmos i/o) 10 note 3 note 3 00 1 enables count operation si1 note 3 so1 sck1 1 operation (input) (cmos output) (input) 1 0 1 sck1 (cmos output) notes 1. be sure to clear bit 5 to 0. 2. these pins can be used as port pins. 3. when only transmission is executed, this pin can be used as p20. remark : dont care pm : port mode register p : output latch of port controls operation of counter of serial clock 7 csie 1 6 dir 5 0 note 1 4 0 3 0 2 0 1 csim 11 0 csim 10 csim1 symbol ff68h address at reset r/w 00h r/w
169 chapter 8 applications of serial interface figure 8-11. format of interrupt timing specification register ( m pd78002, 78014 subseries) notes 1. bit 6 (cld) is a read-only bit. 2. clear sic to 0 when using the wake-up function. 3. cld is 0 when csie0 = 0. caution be sure to clear bits 0 through 3 to 0. remark sva : slave address register csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of the serial operating mode register 0 (csim0) 765432 symbol 10 svam bits of sva used as slave address ff63h 0 sint 0 00 svam sic cld 0 address at reset r/w 00h r/w note 1 0 bits 0 through 7 1 bits 1 through 7 sic selects intcsi0 interrupt source note 2 0 sets csiif0 at end of transfer of serial interface channel 0 1 sets csiif0 on detection of bus release r/w r/w cld level of sck0 pin note 3 0 low level 1 high level r
170 chapter 8 applications of serial interface figure 8-12. format of interrupt timing specification register ( m pd78002y, 78014y subseries) (1/2) r/w wat1 wat0 controls wait and interrupt processing request 0 0 generates interrupt request at rising edge of 8th clock of sck0 (clock output goes into high-impedance state) 0 1 setting prohibited 1 0 used in i 2 c bus mode (8-clock wait). generates interrupt processing request at rising edge of 8th clock of scl (master makes scl output low and waits after outputting 8 clocks. slave makes scl pin low and requests for wait after inputting 8 clocks). 1 1 used in i 2 c bus mode (9-clock wait). generates interrupt processing request at rising edge of 9th clock of scl (master makes scl output low and waits after outputting 9 clocks. slave makes scl pin low and requests for wait after inputting 9 clocks). r/w wrel controls wait release 0 wait release status 1 releases wait status. after wait status has been released, this bit is automatically cleared to 0 (used to release wait status set by wat1 and wat0) r/w clc controls clock level note 2 0 used in i 2 c bus mode. makes output level of scl pin low when serial transfer is not executed 1 used in i 2 c bus mode. makes output level of scl pin high impedance when serial transfer is not executed (clock line goes high). used by master to generate start/stop condition. notes 1. bit 6 (cld) is a read-only bit. 2. clear clc to 0 when the i 2 c bus mode is not used. 765432 symbol 10 ff63h wat0 sint wat1 clc wrel svam sic cld 0 address at reset r/w 00h r/w note 1
171 chapter 8 applications of serial interface figure 8-12. format of interrupt timing specification register ( m pd78002y, 78014y subseries) (2/2) r/w svam bits of sva used as slave address 0 bits 0 through 7 1 bits 1 through 7 r/w sic selects intcsi0 interrupt source note 1 0 sets csiif0 to 1 at end of transfer of serial interface channel 0 1 sets csiif0 to 1 on detection of bus release in the sbi mode, or on detection of stop condition in the i 2 c bus mode r/w cld level of sck0/scl/p27 pin note 2 0 low level 1 high level notes 1. clear sic to 0 when using the wake-up function. 2. cld is 0 when csie0 = 0. remark sva : slave address register csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of the serial operating mode register 0 (csim0)
172 chapter 8 applications of serial interface figure 8-13. format of interrupt timing specification register ( m pd78018f, 78014h subseries) notes 1. bit 6 (cld) is a read-only bit. 2. clear sic to 0 when using the wake-up function in the sbi mode. 3. cld is 0 when csie0 = 0. caution be sure to clear bits 0 through 3 to 0. remark sva : slave address register csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of the serial operating mode register 0 (csim0) 765432 symbol 10 svam bits of sva used as slave address ff63h 0 sint 0 00 svam sic cld 0 address at reset r/w 00h r/w note 1 0 bits 0 through 7 1 bits 1 through 7 sic selects intcsi0 interrupt source note 2 0 sets csiif0 at end of transfer of serial interface channel 0 1 sets csiif0 at end of transfer of serial interface channel 0 or on detection of bus release r/w r/w cld level of sck0 pin note 3 0 low level 1 high level r
173 chapter 8 applications of serial interface figure 8-14. format of interrupt timing specification register ( m pd78018fy subseries) (1/2) r/w wat1 wat0 controls wait and interrupt processing request 0 0 generates interrupt request at rising edge of 8th clock of sck0 (clock output goes into high-impedance state) 0 1 setting prohibited 1 0 used in i 2 c bus mode (8-clock wait). generates interrupt processing request at rising edge of 8th clock of scl (master makes scl output low and waits after outputting 8 clocks. slave makes scl pin low and requests for wait after inputting 8 clocks). 1 1 used in i 2 c bus mode (9-clock wait). generates interrupt processing request at rising edge of 9th clock of scl (master makes scl output low and waits after outputting 9 clocks. slave makes scl pin low and requests for wait after inputting 9 clocks). r/w wrel controls wait release 0 wait release status 1 releases wait status. after wait status has been released, this bit is automatically cleared to 0 (used to release wait status set by wat1 and wat0) r/w clc controls clock level note 2 0 used in i 2 c bus mode. makes output level of scl pin low when serial transfer is not executed 1 used in i 2 c bus mode. makes output level of scl pin high impedance when serial transfer is not executed (clock line goes high). used by master to generate start/stop condition. notes 1. bit 6 (cld) is a read-only bit. 2. clear clc to 0 when the i 2 c bus mode is not used. 765432 symbol 10 ff63h wat0 sint wat1 clc wrel svam sic cld 0 address at reset r/w 00h r/w note 1
174 chapter 8 applications of serial interface figure 8-14. format of interrupt timing specification register ( m pd78018fy subseries) (2/2) r/w svam bits of sva used as slave address 0 bits 0 through 7 1 bits 1 through 7 r/w sic selects intcsi0 interrupt source note 1 0 sets csiif0 to 1 at end of transfer of serial interface channel 0 1 sets csiif0 to 1 at end of transfer of serial interface channel 0 or on detection of stop condition in the i 2 c bus mode r/w cld level of sck0/scl/p27 pin note 2 0 low level 1 high level notes 1. clear sic to 1 when using the wake-up function in the i 2 c mode. 2. cld is 0 when csie0 = 0. remark sva : slave address register csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of the serial operating mode register 0 (csim0)
175 chapter 8 applications of serial interface figure 8-15. format of serial bus interface control register ( m pd78002, 78014, 78018f, 78014h subseries) (1/2) r/w relt used to output bus release signal. when relt = 1, so latch is set to 1. after so latch has been set, this bit is automatically cleared to 0. it is also cleared to 0 when csie = 0. r/w cmdt used to output command signal. when cmdt = 1, so latch is cleared to 0. after so latch has been cleared, this bit is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r reld bus release detection clear condition (reld = 0) set condition (reld = 1) ? on execution of transfer start instruction ? when bus release signal (rel) is detected ? if values of sio0 and sva do not coincide when address is received ? when csie0 = 0 ? at reset input r cmdd command detection clear condition (cmdd = 0) set condition (cmdd = 1) ? on execution of transfer start instruction ? when command signal (cmd) is detected ? when bus release signal (rel) is detected ? when csie0 = 0 ? at reset input r/w ackt outputs acknowledge signal in synchronization with falling edge of sck0 clock immediately after instruction that sets this bit to 1 has been executed. after acknowledge signal has been output, this bit is automatically cleared to 0. acke is cleared to 0. this bit is also cleared to 0 when transfer of serial interface is started and when csie0 = 0. note bits 2, 3, and 6 (reld, cmdd, and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (reld, cmdt, and ackt) are cleared to 0 when they are read after data has been set. 2. csie0: bit 7 of the serial operating mode register 0 (csim0) 765432 symbol 10 ff61h relt sbic cmdt cmdd reld ackt acke ackd bsye address at reset r/w 00h r/w note
176 chapter 8 applications of serial interface figure 8-15. format of serial bus interface control register ( m pd78002, 78014, 78018f, 78014h subseries) (2/2) r/w acke controls acknowledge signal output 0 disables automatic output of acknowledge signal (output by ackt is enabled) 1 before completion acknowledge signal is output in synchronization with falling edge of 9th clock of transfer of sck0 (automatically output when acke = 1) after completion acknowledge signal is output in synchronization with falling edge of sck0 of transfer clock immediately after instruction that sets this bit to 1 has been executed (automatically output when acke = 1). however, this bit is not automatically cleared to 0 after acknowledge signal has been output. r ackd acknowledge detection clear condition (ackd = 0) set condition (ackd = 1) ? falling edge of sck0 clock immediately after ? when acknowledge signal (ack) is detected at busy mode has been released after execution rising edge of sck0 clock after completion of of transfer start instruction transfer ? when csie0 = 0 ? at reset input r/w controls output of synchronization busy signal 0 disables output of busy signal in synchronization with falling edge of sck0 clock immediately after instruction that clears this bit to 0 has been executed 1 outputs busy signal at falling edge of sck0 clock following acknowledge signal note the busy mode can be released by starting serial interface transfer and receiving of an address signal. however, the bsye flag is not cleared to 0. remark csie0: bit 7 of the serial operating mode register 0 (csim0) bsye note
177 chapter 8 applications of serial interface figure 8-16. format of serial bus interface control register ( m pd78002y, 78014y subseries) (1/2) r/w relt used to output bus release signal in sbi mode. used to output stop condition in i 2 c bus mode. when relt = 1, so latch is set to 1. after so latch has been set, this bit is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w cmdt used to ouptut command signal in sbi mode. used to output start condition in i 2 c bus mode. when cmdt = 1, so latch is cleared to 0. after so latch has been cleared, this bit is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r reld stop condition detection clear condition (reld = 0) set condition (reld = 1) ? on execution of transfer start instruction ? when a bus release signal (rel) is detected in ? if values of sio0 and sva do not coincide when sbi mode address is received ? when stop condition is detected in i 2 c bus mode ? when csie0 = 0 ? at reset input r cmdd start condition detection clear condition (cmdd = 0) set condition (cmdd = 1) ? on execution of transfer start instruction ? when a command signal (cmd) is detected in ? when a bus release signal (rel) is detected in sbi mode sbi mode ? when start condition is detected in i 2 c bus mode ? when stop condition is detected in i 2 c bus mode ? when csie0 = 0 ? at reset input r/w ackt in the sbi mode, this bit outputs an acknowledge signal in synchronization with the falling edge of the sck0 clock immediately after the instruction that sets this bit to 1. after output, this bit is automatically cleared to 0. used as acke = 0. also cleared to 0 when transfer by serial interface is started and csie = 0. in the i 2 c mode, this bit makes sda0 (sda1) low immediately after instruction that sets this bit to 1 (ackt = 1) until next scl falls. used to generate ack signal by software when 8-clock wait is selected. cleared to 0 when transfer by serial interface is started and csie0 = 0. note bits 2, 3, and 6 (reld, cmdd, and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (reld, cmdt, and ackt) are cleared to 0 when they are read after data has been set. 2. csie0: bit 7 of the serial operating mode register 0 (csim0) 765432 symbol 10 ff61h relt sbic cmdt cmdd reld ackt acke ackd bsye address at reset r/w 00h r/w note
178 chapter 8 applications of serial interface figure 8-16. format of serial bus interface control register ( m pd78018fy subseries) (2/2) r/w acke controls acknowledge signal output (in sbi mode) 0 disables automatic output of acknowledge signal (output by ackt is enabled) 1 before completion acknowledge signal is output in synchronization with falling edge of 9th clock of transfer of sck0 (automatically output when acke = 1) after completion acknowledge signal is output in synchronization with falling edge of sck0 of transfer clock immediately after instruction that sets this bit to 1 has been executed (automatically output when acke = 1). however, this bit is not automatically cleared to 0 after acknowledge signal has been output. r/w acke controls automatic output of acknowledge signal note 1 (in i 2 c bus mode) 0 disables automatic output of acknowledge signal (output by ackt is enabled). used for transmission or reception with 8-clock wait selected note 2 . 1 enables automatic output of acknowledge signal. acknowledge signal is output in synchronization with falling edge of 9th clock of scl (automatically output when acke = 1). after output, this bit is not automatically cleared to 0. used for reception when 9-clock wait is selected. r ackd acknowledge detection clear condition (ackd = 0) set condition (ackd = 1) ? falling edge of sck0 clock immediately after busy ? when acknowledge signal is detected at rising mode has been released after execution of edge of sck0/scl clock after completion of transfer start instruciton in sbi mode transfer ? on execution of transfer start instruction in i 2 c bus mode ? when csie0 = 0 ? at reset input r/w controls output of synchronization busy signal 0 in the sbi mode, this bit disables output of busy signal in synchronization with falling edge of sck0/scl clock immediately after instruction that clears this bit to 0 has been executed. be sure to clear bsye to 0 in the i 2 c bus mode. 1 in the sbi mode, this bit outputs busy signal at falling edge of sck0/scl clock following acknowl- edge signal. notes 1. set this bit before starting transfer. 2. output the acknowledge signal on reception by using ackt when 8-clock wait is selected. 3. the busy status can be released by starting transfer of serial interface or receiving an address signal. however, bsye is not cleared to 0. remark csie0: bit 7 of the serial operating mode register 0 (csim0) bsye note 3
179 chapter 8 applications of serial interface figure 8-17. format of serial bus interface control register ( m pd78018fy subseries) (1/2) r/w relt used to output stop condition in i 2 c bus mode. when relt = 1, so latch is set to 1. after so latch has been set, this bit is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r/w cmdt used to output start condition in i 2 c bus mode. when cmdt = 1, so latch is cleared to 0. after so latch has been cleared, this bit is automatically cleared to 0. it is also cleared to 0 when csie0 = 0. r reld stop condition detection clear condition (reld = 0) set condition (reld = 1) ? on execution of transfer start instruction ? when stop condition is detected in i 2 c bus mode ? if values of sio0 and sva do not coincide when address is received ? when csie0 = 0 ? at reset input r cmdd start condition detection clear condition (cmdd = 0) set condition (cmdd = 1) ? on execution of transfer start instruction ? when start condition is detected in i 2 c bus mode ? when stop condition is detected in i 2 c bus mode ? when csie0 = 0 ? at reset input r/w ackt makes sda0 (sda1) low immediately after instruction that sets this bit to 1 (ackt = 1) until next scl falls. used to generate ack signal by software when 8-clock wait is selected. cleared to 0 when transfer by serial interface is started and csie0 = 0 note bits 2, 3, and 6 (reld, cmdd, and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (reld, cmdt, and ackt) are cleared to 0 when they are read after data has been set. 2. csie0: bit 7 of the serial operating mode register 0 (csim0) 765432 symbol 10 ff61h relt sbic cmdt cmdd reld ackt acke ackd bsye address at reset r/w 00h r/w note
180 chapter 8 applications of serial interface figure 8-17. format of serial bus interface control register ( m pd78018fy subseries) (2/2) r/w acke controls automatic output of acknowledge signal note 1 0 disables automatic output of acknowledge signal (output by ackt is enabled). used for transmission or reception with 8-clock wait selected note 2 . 1 enables automatic output of acknowledge signal. acknowledge signal is output in synchronization with falling edge of 9th clock of scl (automatically output when acke = 1). after output, this bit is not automatically cleared to 0. used for reception when 9-clock wait is selected. r ackd acknowledge detection clear condition (ackd = 0) set condition (ackd = 1) ? on execution of transfer start instruction ? when acknowledge signal is detected at rising ? when csie0 = 0 edge of scl clock after completion of transfer ? at reset input r/w controls transmission n-ch open drain output in i 2 c bus mode note 4 0 enables output (transmission) 1 disables output (reception) notes 1. set this bit before starting transfer. 2. output the acknowledge signal on reception by using ackt when 8-clock wait is selected. 3. the wait status can be released by starting transfer of serial interface or receiving an address signal. however, bsye is not cleared to 0. 4. be sure to set bsye to 1 when using the wake-up function. remark csie0: bit 7 of the serial operating mode register 0 (csim0) bsye note 3
181 chapter 8 applications of serial interface figure 8-18. format of automatic data transmit/receive control register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries only) notes 1. bits 3 and 4 (trf and err) are read-only bits. 2. identify the end of automatic transmission/reception by using trf instead of csiif1. (interrupt request flag) caution when external clock input is selected by clearing bit 1 (csim11) of the serial operating mode register 1 (csim1) to 0, clear bits 1 and 2 (busy1 and strb) of adtc to 0, 0. remark : dont care 765432 symbol 10 ff69h busy0 adtc busy1 trf strb err erce arld re address at reset r/w 00h r/w note 1 busy1 controls busy input 0 does not use busy input 1 enables busy input (active high) busy0 0 1 enables busy input (low active) 1 r/w strb controls strobe output 0 disables strobe output 1 enables strobe output r/w trf status of automatic transmit/receive function note 2 0 detects end of automatic transmission/reception (0 when automatic tansmission/reception is stopped or when arld = 0) 1 automatic transmission/reception in progress (1 when sio1 is written) r err detects error of automatic transmit/receive function 0 no error on automatic tansmission/reception (0 when 1 is written to sio1) 1 error on automatic tansmission/reception r erce controls error check of automatic transmit/receive function 0 disables error check on automatic transmission/reception 1 enables error check on automatic transmission/reception (only when busy1 = 1) r/w arld selects operation mode of automatic transmit/receive function 0 single mode 1 repetitive mode r/w re controls reception of automatic transmit/receive function 0 disables reception 1 enables reception r/w
182 chapter 8 applications of serial interface figure 8-19. format of automatic data transmit/receive interval specification register ( m pd78018f, 78018fy, 78014h subseries only) (1/2) adti7 controls interval time of data transfer 0 does not control interval time by adti note 1 1 controls interval time by adti (adti0 through adti4) adti4 adti3 adti2 adti1 adti0 specifies interval time of data transfer (f x = 10.0 mhz) minimum value note 2 maximum value note 2 0 0 0 0 0 18.4 m s + 0.5/f sck 20.0 m s + 1.5/f sck 0 0 0 0 1 31.2 m s + 0.5/f sck 32.8 m s + 1.5/f sck 0 0 0 1 0 44.0 m s + 0.5/f sck 45.6 m s + 1.5/f sck 0 0 0 1 1 56.8 m s + 0.5/f sck 58.4 m s + 1.5/f sck 0 0 1 0 0 69.6 m s + 0.5/f sck 71.2 m s + 1.5/f sck 0 0 1 0 1 82.4 m s + 0.5/f sck 84.0 m s + 1.5/f sck 0 0 1 1 0 95.2 m s + 0.5/f sck 96.8 m s + 1.5/f sck 0 0 1 1 1 108.0 m s + 0.5/f sck 109.6 m s + 1.5/f sck 0 1 0 0 0 120.8 m s + 0.5/f sck 122.4 m s + 1.5/f sck 0 1 0 0 1 133.6 m s + 0.5/f sck 135.2 m s + 1.5/f sck 0 1 0 1 0 146.4 m s + 0.5/f sck 148.0 m s + 1.5/f sck 0 1 0 1 1 159.2 m s + 0.5/f sck 160.8 m s + 1.5/f sck 0 1 1 0 0 172.0 m s + 0.5/f sck 173.6 m s + 1.5/f sck 0 1 1 0 1 184.8 m s + 0.5/f sck 186.4 m s + 1.5/f sck 0 1 1 1 0 197.6 m s + 0.5/f sck 199.2 m s + 1.5/f sck 0 1 1 1 1 210.4 m s + 0.5/f sck 212.0 m s + 1.5/f sck notes 1. the interval time is dependent on only the cpu processing. 2. the interval time of data transfer includes an error. the minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to adti0 through adti4). however, if the minimum value calculated by the expression below is less than 2/f sck , the minimum interval time is 2/f sck . minimum value = (n + 1) + + maximum value = (n + 1) + + 2 7 f x 56 f x 0.5 f sck 2 7 f x 72 f x 1.5 f sck 765432 symbol 10 ff6bh adti0 adti adti1 adti3 adti2 adti4 0 0 adti7 address at reset r/w 00h r/w
183 chapter 8 applications of serial interface cautions 1. do not write adti during automatic transmission/reception operation. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling interval time of data transfer by automatic transmission/reception using adti, the busy control option is invalid. remarks 1. f x : main system clock oscillation frequency 2. f sck : serial clock frequency
184 chapter 8 applications of serial interface figure 8-19. format of automatic data transmit/receive interval specification register ( m pd78018f, 78018fy, 78014h subseries only) (2/2) adti4 adti3 adti2 adti1 adti0 specifies interval time of data transfer (f x = 10.0 mhz) minimum value note maximum value note 1 0 0 0 0 223.2 m s + 0.5/f sck 224.8 m s + 1.5/f sck 1 0 0 0 1 236.0 m s + 0.5/f sck 237.6 m s + 1.5/f sck 1 0 0 1 0 248.8 m s + 0.5/f sck 250.4 m s + 1.5/f sck 1 0 0 1 1 261.6 m s + 0.5/f sck 263.2 m s + 1.5/f sck 1 0 1 0 0 274.4 m s + 0.5/f sck 276.0 m s + 1.5/f sck 1 0 1 0 1 287.2 m s + 0.5/f sck 288.8 m s + 1.5/f sck 1 0 1 1 0 300.0 m s + 0.5/f sck 301.6 m s + 1.5/f sck 1 0 1 1 1 312.8 m s + 0.5/f sck 314.4 m s + 1.5/f sck 1 1 0 0 0 325.6 m s + 0.5/f sck 327.2 m s + 1.5/f sck 1 1 0 0 1 338.4 m s + 0.5/f sck 340.0 m s + 1.5/f sck 1 1 0 1 0 351.2 m s + 0.5/f sck 352.8 m s + 1.5/f sck 1 1 0 1 1 364.0 m s + 0.5/f sck 365.6 m s + 1.5/f sck 1 1 1 0 0 376.8 m s + 0.5/f sck 378.4 m s + 1.5/f sck 1 1 1 0 1 389.6 m s + 0.5/f sck 391.2 m s + 1.5/f sck 1 1 1 1 0 402.4 m s + 0.5/f sck 404.0 m s + 1.5/f sck 1 1 1 1 1 415.2 m s + 0.5/f sck 416.8 m s + 1.5/f sck note the interval time of data transfer includes an error margin. the minimum and maximum values of the interval time for data transfer can be calculated by the following expressions (where n is the value set to adti0 through adti4). however, if the minimum value calculated by the expression below is less than 2/f sck , the minimum interval time is 2/f sck . minimum value = (n + 1) + + maximum value = (n + 1) + + cautions 1. do not write adti during automatic transfer/reception operation. 2. be sure to clear bits 5 and 6 to 0. 3. when controlling interval time of data transfer by automatic transmission/reception using adti, the busy control option is invalid. remarks 1. f x : main system clock oscillation frequency 2. f sck : serial clock frequency 2 7 f x 56 f x 0.5 f sck 2 7 f x 72 f x 1.5 f sck 765432 symbol 10 ff6bh adti0 adti adti1 adti3 adti2 adti4 0 0 adti7 address at reset r/w 00h r/w
185 chapter 8 applications of serial interface 8.1 interface with eeprom tm ( m pd6252) the m pd6252 note is a 2048-bit eeprom which can be electrically written or erased. to write or read data to or from the m pd6252, the 3-wire serial interface is used. note m pd6252 is for maintenance use. figure 8-20. pin configuration of m pd6252 1 ce 2 ic 3 ic 4 gnd v dd 8 cs 7 scl 6 sda 5
186 chapter 8 applications of serial interface table 8-3. pin function of m pd6252 pin number pin name i/o function 1 ce cmos input keep this pin high during data transfer. caution do not change the level of this pin from high to low during data transfer. to change the level of this pin from high to low, make sure that the cs pin (pin 7) is low. by making both the ce and cs pins low, you can set the standby status in which the power consumption is reduced. 2 ic C fix the ic pins to the high or low level via resistor. 3 4 gnd C ground 5 sda cmos input/ data input/output pin. n-ch open-drain because this pin is an n-ch open-drain i/o pin, externally pull it up with a resistor. output 6 scl cmos input inputs a clock for data transfer. 7 cs cmos input chip select pin. when this pin is high, the m pd6252 is enabled to operate. when it is low, memory cells cannot be read or written. when the level of this pin is changed from high to low with the scl pin high, the operation of the serial bus interface is started. to end the operation of the serial bus interface, change the level of this pin from high to low. 8v dd C positive power: +5 v 10% sda
187 chapter 8 applications of serial interface 8.1.1 communication in 2-wire serial i/o mode the 3-wire mode of the m pd6252 note is implemented by serial clock (scl), data (sda), and chip select (cs) lines. excluding the handshaking line, therefore, only two lines, clock and data lines, are necessary for interfacing. to interface the m pd6252 with a 78k/0 series microcontroller, the 2-wire serial i/o mode is used. in the example shown in this section, the m pd78014 subseries is used. note m pd6252 is for maintenance use. figure 8-21. example of connection of m pd6252 table 8-4 and figure 8-22 shows the commands to write and read data to/from the m pd6252 and communication format. table 8-4. m pd6252 commands command name command operation random write 00000000b [00h] transfers write data after setting an 8-bit word address (wa). up to 3 bytes of write msb data can be set successively. c 7 -c 0 correspondence between word address and data wa data of first byte wa+1 data of second byte wa+2 data of third byte the write operation is executed in the internal write cycle after the cs pin has gone low. current read 10000000b [80h] transfers the contents of memory specified by the word address (wa) (current msb address) specified when the command is set, to the read data buffer. each time 8 c 7 -c 0 bits of data have been read from the sda pin, the word address (wa) is incremented, and the corresponding memory contents are transferred to the data buffer. random read 11000000b [c0h] executes data read starting from a set word address (wa) after the word address has msb been set. c 7 -c 0 the difference from current read is that this command sets a word address (wa) after it has been executed. after the word address has been set, this command performs the same operation as current read. pd78014 sck0 scl m pd6252 m sb1 sda p32 cs ce v dd v dd
188 chapter 8 applications of serial interface figure 8-22. communication format of m pd6252 (1) random write (2) current read (3) random read cs sda scl c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 wa 7 wa 6 wa 5 wa 4 wa 3 wa 2 wa 1 wa 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd byte wb flag output write is executed by making cs in low with scl pin high. wa is last written address + 1 and is retained (current address) (issuance of stp). wa input command input write data input (wa) (wa + 1) (wa + 2) internal wa sda mode starts by making cs pin high when scl pin is high (issuance of sta). wa retains input value until stp is detected, and is incremented each time 1 byte is written in the internal write cycle after stp has been detected. data of 1st byte is written to memory addressed by wa. wb flag is retained while eight clocks are input to scl pin. in out in wa + 1 to wa + 3 00000000 current address wa cs sda scl c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 0 d 7 d 6 d 2 d 0 wb flag output current address command input read data (wa) (wa + 1) internal wa sda mode in out out wa + n + 1 10000000 current address = wa wa+n (wa + 2) (wa + n) operation ends by making cs pin high with scl pin high. wa is last read address + 1 and retained (current address) (issuance of stp) wa+2 wa+1 d 1 1st byte 3rd byte operation ends if cs pin is made low with scl pin high (issuance of stp). wa is last read address + 1 and retained. cs sda scl c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 wa 7 wa 6 wa 5 wa 4 wa 3 wa 2 wa 1 wa 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 wb flag output wa input (wa) internal wa sda mode in out in wa + n + 1 11000000 current address wa d 7 d 1 d 0 (wa+1) ?(wa+n) wb flag is retained while 8 clocks are input to scl pin. starts by making cs pin high with scl pin high (issuance of sta). contents of wa are read as data of first byte. contents of wa+1, ?wa+n are sequentially read each time 1 byte has been read. wa+1 wa+n out
189 chapter 8 applications of serial interface steps <1> through <5> below are the operating procedure of the m pd6252. in this example, the number of data to be written or read per interface operation is fixed to 1 byte. if the m pd6252 is in the write busy (wb) status when interfaced, the busy flag is set. <1> make the cs pin (p32) high to start interfacing. <2> transmit the write or read command. <3> receive the data of write busy. if interfacing the m pd6252 is enabled, 00h is received. if a code other than 00h is received, it is judged that the m pd6252 is in the write busy status. in this case, communication is stopped. <4> transfer the data corresponding to the command. <5> make the cs pin (p32) low to end the communication. (1) description of package t3_6252 : m pd6252 transfer subroutine name rwrite : random write command value rread : random read command value cread : current read command value wadat : word address storage area trndat : transmit data storage area rcvdat : receive data storage area cmddat : command data storage area busyfg : busy status test flag cs6252 : cs pin (p32) of m pd6252 a name usage attribute bytes waadr stores word address (before start of transfer) saddr 1 trndat stores transmit data (before start of transfer) rcvdat stores receive data (after end of transfer) cmddat stores command data (before start of transfer)
190 chapter 8 applications of serial interface name usage busyfg sets write busy status 1 level 3 bytes ? serial interface channel 0 ? p32 ? setting of serial interface channel 0 selects 2-wire serial i/o mode and sb1 pin csim0 = #10011011b ? serial clock f x /2 5 tcl3 = # 1001b ? makes sb1 latch high relt = 1 set the necessary data corresponding to the commands and call t3_6252. after execution returns from the subroutine, the busy flag (busyfg) is tested. if the busy flag is set, transfer is not executed. it is therefore necessary to execute transfer again. in the receive mode, the receive data is stored rcvdat after execution has returned from the subroutine.
191 chapter 8 applications of serial interface (2) example of use extrn rwrite,rread,cread extrn wadat,trndat,rcvdat,cmddat,t3_6252 extbit busyfg,cs6252 csim0=#10011011b tcl3=#10011001b clr1 sb0 clr1 cs6252 clr1 pm3.2 cmddat=a wadat=a trndat=a repeat clr1 busyfg call !t3_6252 until_bit(!busyfg) a=rcvdat . . . . . . . . . . . . . . . . ; sets 2-wire serial i/o mode and sb1 pin ; sets sck0 = 262 khz ; makes cs of m pd6252 low sets each data to memory until: not write busy clears busy flag calls t3_6252 loads receive data
192 chapter 8 applications of serial interface (3) spd chart t3_6252 clears busy flag issues start bit transfers command while: waits for end of transfer (csiif0 = 0) receives busy signal while: waits for end of transfer (csiif0 = 0) if: not wb status (sio0 = 00h) then else case: cmddat of: rwrite transfers word address while: waits for end of transfer transfers data while: waits for end of transfer break of: rread transfers word address while: waits for end of transfer of: cread receives data while: waits for end of transfer stores receive data to memory sets busy status sets busyfg issues stop bit
193 chapter 8 applications of serial interface (4) program list public rwrite,rread,cread public wadat,trndat,rcvdat,cmddat,t3_6252 public busyfg,cs6252 csi_dat dseg saddr wadat: ds 1 trndat: ds 1 rcvdat: ds 1 cmddat: ds 1 csi_flg bseg busyfg dbit rwrite equ 00h rread equ 0c0h cread equ 080h cs6252 equ 0ff03h.2 csi_seg cseg ;************************************* ;* m pd6252 (3-wire) communication ;************************************* t3_6252: clr1 busyfg set1 cs6252 si00=cmddat (a) while_bit(!csiif0) endw clr1 csiif0 sio0=#0ffh while_bit(!csiif0) endw clr1 csiif0 if(sio0==#00h) switch (cmddat) case rwrite: sio0=wadat (a) while_bit(!csiif0) endw clr1 csiif0 sio0=trndat (a) while_bit(!csiif0) endw clr1 csiif0 break case rread: sio0=wadat (a) while_bit(!csiif0) endw clr1 csiif0 case cread: sio0=#0ffh while_bit(!csiif0) endw clr1 csiif0 rcvdat=sio0 (a) ends ; word address storage area ; transmit data storage area ; receive data storage area ; command data storage area ; sets busy status ; random write mode ; random read mode ; current read mode ; 0ff03h=port3 ; issues start bit ; transfers command ; waits for end of transfer ; starts reception of busy signal ; waits for end of transfer ; busy check ; transfers word address ; waits for end of transfer ; starts data transfer ; waits for end of transfer ; transfers word address ; waits for end of transfer ; starts data reception ; waits for end of transfer ; stores receive data
194 chapter 8 applications of serial interface ; sets busy status else set1 busyfg endif clr1 cs6252 ret
195 chapter 8 applications of serial interface 8.1.2 communication in i 2 c bus mode in the 2-wire mode of the m pd6252 note , two lines, serial clock (scl) and data (sda) lines are used for communication. this mode conforms to the communication format of i 2 c. therefore, the i 2 c mode is selected when communicating with the m pd6252 by using the m pd78002y, 78014y, or 78018fy subseries. in the example shown in this section, the m pd78014y subseries is used. note m pd6252 is for maintenance use. figure 8-23. example of connection between m pd6252 and i 2 c bus mode figure 8-24 shows the communication format in which data is written to or read from the m pd6252. pd78014y sda0 (sda1) scl sda scl sda scl m pd6252 m a 1 = 0 a 2 = 0 a 1 = 1 a 2 = 0 sda scl a 1 = 0 a 2 = 1 sda scl a 1 = 1 a 2 = 1
196 chapter 8 applications of serial interface figure 8-24. m pd6252 operation timing (a) transmission to m pd6252 (b) reception from m pd6252 (without word address specification) (c) reception from m pd6252 (with word address specification) wa 7 wa 6 wa 5 wa 4 wa 3 wa 2 wa 1 wa 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 start condition d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 101 0a 2 a 1 00 ack ack ack ack sda scl write stop condition write data write data slave address r/w command word address d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 start condition d 0 101 0a 2 a 1 01 ack ack sda scl read stop condition read data slave address r/w command read data wa 7 wa 6 wa 5 wa 4 wa 3 wa 2 wa 1 wa 0 start condition 101 0a 2 a 1 00 ack ack sda scl write slave address r/w command read data slave address r/w command word address a 2 a 1 10 101 ack start condition read 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 stop condition
197 chapter 8 applications of serial interface steps <1> through <5> below are the communication procedure of the m pd6252. in this example, the number of data to be written or read is fixed to 1 byte. if the master receives data in the i 2 c bus format, and if it has received the last data, the ack signal is not output. because the master does not output the ack signal in this example, bit 5 (acke) of serial bus interface control register (sbic) is always 0. <1> set a start condition to start communication. fall the data with the serial clock high. <2> transmit the slave address value (bits 1 through 7) of the m pd6252 and write (bit 0 = 0)/read (bit 0 = 1) select bit. 1 0 1 0 a 2 a 1 0 r / w slave address r/w selection 7-bit (bits 7 through 1) 1 bit (bit 0) remark a 2 and a 1 are set by external pins. <3> transfer the data. ? in transmission mode (i) transmit the word address of the m pd6252. (ii) transmit the write data. ? in reception mode receive the read data. <4> set an end condition to end the communication. rise the data with the serial clock high. <5> because a word address is specified only in the write mode, to read data by specifying an address, the address must be specified by once setting the write mode. if the m pd6252 does not return the ack signal during data transfer, communication is stopped. the start and end conditions are set by bit 3 (clc) of interrupt timing specification register (sint) when the serial clock is manipulated, and by relt and cmdt (bits 0 and 1 of sbic) when data is manipulated.
198 chapter 8 applications of serial interface (1) description of package t2_6252 : m pd6252 transfer subroutine name waadr : word address storage area trndat : transmit data storage area rcvdat : receive data storage area slvadr : slave address storage area busyfg : busy status test flag wrchg : write ? read mode change flag errfg : error status test flag a name usage attribute bytes waadr stores word address (before start of transfer) saddr 1 trndat stores transmit data (before start of transfer) rcvdat stores receive data (after end of transfer) slvadr stores slave address name usage busyfg sets write busy status wrchg changes write mode to read mode errfg sets error status 1 level 2 bytes serial interface 0 ? setting of serial interface channel 0 selects 2-wire serial i/o mode and sb0 pin csim0 = #10011011b ? selects serial clock f x /2 4 and 16 tcl3 = # 1000b ? generates interrupts at rising edge of 9th sint = #00001011b serial clock and sets clock line to high level ? set the necessary data corresponding to the commands and call t2_6252. in the reception mode, the receive data is stored to rcvdat after execution has returned from the subroutine. ? if the serial clock is low (busy status) when communication is started or if ack cannot be received during data transfer, the busyfg and errfg are set. test and clear these flags with the main processing.
199 chapter 8 applications of serial interface (2) example of use extrn waadr,trndat,rcvdat,slvadr,t2_6252 extbit busyfg,wrchg,errfg set1 sb0 csim0=#10011011b sint=#00001011b tcl3=#10001000b set1 relt set1 sck0 clr1 sb0 waadr=a trndat=a slvadr=a call !t2_6252 if_bit(busyfg) clr1 busyfg endif if|bit(errfg) clr1 errfg endif ; serial interface 2-wire, sb0 ; sets i 2 c mode ; sck = 32.7 khz sets data calls t2_6252 (if: sets busyfg) clears busyfg to busy processing (if: sets errfg) clears errfg to error processing . . . . . . . . . . . . . . . . . . . .
200 chapter 8 applications of serial interface (3) spd chart if: sck0 = low t2_6252 sets busy status then sets busyfg else issues start bit stabit transmits slave address while: waits for end of transfer (csiif0 = 0) if: ack signal not detected sets error status then else sets errfg if: transmit mode then transmits word address of pd6252 m while: waits for end of transfer if: ack signal not detected then sets error status else sets errfg if: changes to read mode then while: sck0 = high outputs high level in order of data and clock changes slave address to read mode goto stabit else transmits data while: waits for end of transfer if: ack signal not detected then sets error status sets errfg receives data else while: waits for end of transfer stores receive data to memory outputs low level in order of clock and data issues stop bit
201 chapter 8 applications of serial interface (4) program list public waadr,trndat,rcvdat,slvadr,t2_6252 public busyfg,wrchg,errfg csi_dat dseg saddr waadr: ds 1 trndat: ds 1 rcvdat: ds 1 slvadr: ds 1 csi_flg bseg busyfg dbit wrchg dbit errfg dbit sck0 equ p2.7 csi_seg cseg ;************************************* ;* m pd6252 (2-wire) communication ;************************************* t2_6252: if_bit(!cld) set1 busyfg else stabit: set1 cmdt nop nop nop nop nop clr1 clc sio0=slvadr (a) while_bit(!csiif0) endw clr1 csiif0 if_bit(!ackd) set1 errfg elseif_bit(!slvadr.0) si00=waadr (a) while_bit(!csiif0) endw clr1 csiif0 if_bit(!ackd) set1 errfg elseif_bit(wrchg) while_bit(cld) endw set1 relt set1 clc while_bit(!cld) endw nop nop nop nop nop nop nop nop set1 slvadr.0 goto stabit else ; word address storage area ; transmit data storage area ; receive data storage area ; salve address storage area ; sets busy status ; changes mode ; sets error status ; busy status ; issues start bit ; waits for start bit valid width ; changes clock to low level ; starts transmitting slave address ; waits for end of transfer ; ack signal not detected ; transmission mode ; starts transmitting word address ; waits for end of transfer ; ack signal not detected ; checks high level of clock ; waits for high level valid width of clock ; changes to read mode address
202 chapter 8 applications of serial interface extrn waadr,trndat,rcvdat,slvadr,t2_6252 extbit busyfg,wrchg,errfg set1 sb0 csim0=#10011011b sint=#00001011b tcl3=#10001000b set1 relt set1 sck0 clr1 sb0 waadr=a trndat=a slvadr=a call !t2_6252 if_bit(busyfg) clr1 busyfg endif if|bit(errfg) clr1 errfg endif ; serial interface 2-wire, sb0 ; sets i 2 c mode ; sck = 32.7 khz . . . . . . . . . . . .
203 chapter 8 applications of serial interface (5) limitations when i 2 c bus mode is used ( m pd78002y and 78014y series) the following limits apply to the m pd78002y and 78014y subseries. (a) when using microcontroller as master device in i 2 c bus mode applicable model: m pd78p014y description: if the rise time of scl is longer than 1/32 of the transfer clock cycle when the master device outputs scl, the scl output may be stopped or whisker may occur. the rise time means the time required for the scl signal line to reach 0.8 v dd or more after the master device has started communication. therefore, the rise time includes the time during which the master device tries to communicate but the slave device makes scl low because of wait control.
204 chapter 8 applications of serial interface (b) when using microcontroller as slave device in i 2 c bus mode applicable models: m pd78001by, 78002by, 78011by, 78012by, 78013y, 78014y, 78p014y description: when all the following conditions are satisfied, none of the slaves in the system can transmit data. ? if the m pd78002y or 78014y subseries is used as a slave device in the i 2 c bus mode ? if the master outputs a stop condition on completion of transmission to the m pd78002y or 78014y subseries (= slave reception). ? if communication following the master transmission (= slave reception) to the m pd78002y or 78014y subseries is a master reception (= slave transmission) request to any unit. the m pd78002y and 78014y subseries writes a communication start command to the serial i/o shift register 0 (sio0). when these microcontrollers receive data, they write ffh to sio0 to turn off the n-ch open-drain output for transmission. if the master device makes scl high to output a start condition or stop condition after the m pd78002y or 78014y subseries has written ffh to sio0, the m pd78002y or 78014y at the slave side shifts the contents of sio0. as a result, ffh, which has been written as a start command, is shifted, and the lsb of sio0 becomes equal to the level of sda0 (sda1). when sda0 (sda1) is made low and scl is made high, as shown in the figure below, so that the master device outputs a stop condition, the value of sio0 is changed to feh (lsb is 0). therefore, the lsb of the value received next is always 0. because the value received after the stop condition information is considered as a slave address field, the lsb (transfer direction specification bit) of the slave address field is always 0 (slave reception) regardless of the output data of the master. transfer line processing by slave device scl sda0 (sda1) program processing sio0 stop condition start condition this bit is always 0. sio0 ? ffh feh chan g ed to feh here.
205 chapter 8 applications of serial interface preventive measure : in a system where the timing to output a stop condition to the m pd78002y or 78014y subseries (where the number of data communicated between the m pd78002y or 78014y subseries and master is determined), the problem discussed in (b) above can be avoided in software. set bit 5 (wup) of the serial operation mode register 0 (csim0) of the slave device to 1 and the serial i/o shift register 0 (sio0) to ffh before the stop condition is output. in this way, the wake-up function is effected on the slave address field output next by the master device, the n-ch open-drain output is automatically turned off, and the receive data of the slave device is not longer affected. transfer line processing by slave device scl sda0 (sda1) program processing sio0 stop condition start condition pd78002y and 78014y subseries do not affect this bit. wup ? 1 ffh sio0 ? ffh m
206 chapter 8 applications of serial interface (6) limitation when using i 2 c bus mode ( m pd78018fy subseries) the following limitation applies when the m pd78018fy subseries is used. ? when the device is used as a slave device in the i 2 c bus mode applicable models: m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy, 78018fy, 78p018fy description: if the wake-up function is executed (by setting the wup flag (bit 5 of serial operation mode register 0 (csim0) to 1) in the serial transfer status note , the data between other slave device and the master devices is checked as an address. if that data coincides with the slave address of the m pd78018fy subseries, therefore, the m pd78018fy subseries takes part in communication, destroying the communication data. note the serial transfer status is the status from when the serial i/o shift register 0 (sio0) has been written until the interrupt request flag (csiif0) is set to 1 by completion of serial transfer. preventive measures: the above problem can be prevented by modifying the program. before executing the wake-up function, execute the following program that clears the serial transfer status. when executing the wake-up function, do not execute an instruction that writes data to sio0. even if such an instruction is executed, data can be received when the wake-up function is executed. this program is to clear the serial transfer status. to clear the serial transfer status, serial interface channel 0 must be stopped (by clearing the csie0 flag (bit 7 of the serial operation mode register (csim0) to 0). if the serial interface channel 0 is stopped in the i 2 c bus mode, however, the scl pin outputs a high level and the sda0 (sda1) pin outputs a low level, affecting communication on the i 2 c bus. therefore, this program allows the scl and sda0 (sda1) pin to go into a high- impedance state to prevent the i 2 c bus from being affected. note that, in this example, the serial data input/output pin is sda0 (/p25). if sda1 (/p26) is used as the serial data input/output pin, take p2.5 and pm2.5 in the program as p2.6 and pm2.6.
207 chapter 8 applications of serial interface ? example of program that clears serial transfer status set1 p2.5 ; <1> set1 pm2.5 ; <2> set1 pm2.7 ; <3> clr1 csie0 ; <4> set1 csie0 ; <5> set1 relt ; <6> clr1 pm2.7 ; <7> clr1 p2.5 ; <8> clr1 pm2.5 ; <9> <1> when the i 2 c bus mode is restored by instruction <5>, the sda0 pin does not output a low level. the output of the sda0 pin goes into a high-impedance state. <2> the p25(/sda0) pin is set in the input mode to prevent the sda0 line from being affected when the port mode is set by instruction <4>. the p25 pin is set in the input mode when instruction <2> is executed. <3> the p27 (/scl) pin is set in the input mode to prevent the scl line from being affected when the port mode is set by instruction <4>. the p27 pin is set in the input mode when instruction <3> is executed. <4> the i 2 c bus mode is changed to the port mode. <5> the port mode is changed to the i 2 c bus mode. <6> instruction <8> prevents the sda0 pin from outputting a low level. <7> the p27 pin is set in the output mode because it must be in the output mode in the i 2 c bus mode. <8> the output latch of the p25 pin is cleared to 0 because it must be cleared to 0 in the i 2 c bus mode. <9> the p25 pin is set in the output mode because it must be in the output mode in the i 2 c bus mode. remark relt: bit 0 of serial bus interface control register (sbic)
208 chapter 8 applications of serial interface 8.2 interface with osd lsi ( m pd6451a) the osd (on screen display) lsi m pd6451a displays the program information of a vcr and tv channels on a display when used in combination with a microcontroller. the m pd6451a is interface with four lines: data, clk, stb, and busy. in the example shown in this section, the m pd78014 subseries is used to interface the m pd6451a. figure 8-25. example of connecting m pd6451a figure 8-26. communication format of m pd6451a the strobe signal (stb) is output and busy signal (busy) is tested automatically by the serial interface channel 1 of the 78k/0 series to establish handshaking with and to interface the m pd6451a. to match the communication format of the m pd6451a, the m pd78014 subseries is set in a mode in which output of the strobe signal and input of the busy signal (high active) are enabled. by setting the transmit data (32 bytes max) in a buffer area (fac0h through fadfh) and the number of transmit data to the automatic data transmit/receive address pointer (adtp), you can automatically transmit plural data successively. sck1 so1 stb busy do7 do6 do5 do4 do3 do2 do1 do0 pd78014 sck1 clk m pd6451a m rgb so1 data stb stb busy busy display rgb
209 chapter 8 applications of serial interface (1) description of package tr6451 : m pd6451a transfer subroutine name dtval : number of transmit data setting area a name usage attribute bytes dtval stores number of transmit data saddr 1 1 level 2 bytes ? serial interface channel 1 ? setting of serial interface channel 1 enables automatic transmission/reception with msb first csim1 = #10100011b enables busy input (high active) and strobe output in single mode adtc = #00000110b ? interval time of data transfer adti = #00000000b ? serial clock f x /2 5 tcl3 = #1001 b ? makes p22 output latch high ? sets p21, p22, and p23 in output mode and p24 in input mode pm2 = # 1000 b set the data to be transmitted to the buffer ram (starting from the highest address), and the number of data to be transmitted to dtval, and call tr6451. you can check the end of data transfer by testing the bit 3 (trf) of the automatic data transfer/reception control register (adtc).
210 chapter 8 applications of serial interface (2) example of use extrn tr6451,dtval sck1 equ p2.2 p2=#00000100b pm2=#11110001b csim1=#10100011b tcl3=#10011001b adtc=#00000110b adti=#00000000b de=#table1 hl=#0fac0h b=32 while(b>#0) b C C [hl+b]=[de] (a) de++ endw datval=#32 call !tr6451 while_bit(trf) endw . . . . . . . . ; sets automatic transfer/reception function ; sck1 = 262 khz ; enable strobe and busy signals ; interval time of data transfer ; sets table reference address of transmit data ; sets first address of buffer ram ; sets number of data to be transmitted ; transfers transmit data to buffer ram ; sets number of data to be transmitted ; waits for end of transfer sets data to buffer ram sets number of data to be transmitted to dtval calls tr6451 while: waits for end of transfer
211 chapter 8 applications of serial interface table1: db 11111111b db 01000000b db 11000000b db 10000000b db 11111100b db 11101001b db 10001100b db 11011011b db 10010101b db 10100000b db 07h db 08h db 1bh db 6dh db 00h db 10h db 11h db 20h db 20h db 1ch db 19h db 13h db 11h db 24h db 19h db 00h db 1eh db 10h db 1eh db 00h db 24h db 15h remark for the command and data of the output table data, refer to m pd6451a data sheet (document no. ic- 2337) . ; power-on reset, command 1 ; vertical address 0 ; horizontal address 0 ; character size ; command 0 ; turns lc transmission on, blinking off, display on ; turns blinking on. character: red ; color specification, background filled in cyan ; number of display lines: 5 ; number of display digits: 0 ;7 ;8 ;k ;/ ;0 ;a ;p ;p ;l ;i ;c ;a ;t ;i ;o ;n ;n ;o ;t ;e
212 chapter 8 applications of serial interface (3) spd chart (4) program list public tr6451,dtval csi_dat dseg saddr dtval: ds 1 csi_seg cseg ;************************************* ;* m pd6451a communication ;************************************* tr6451: a=dtval a e e adtp=a sio1=#0ffh ret ; number of data setting area ; sets number of data ; starts transfer tr6451 sets (number of data to be transmitted ?1) to adtp sets status before transfer starts transfer
213 chapter 8 applications of serial interface 8.3 interface in sbi mode the 78k/0 series has an sbi mode conforming to nec serial bus format. in this mode, one master cpu can communicate with two or more slave cpus by using two lines: clock and data. in the example shown in this section, the m pd78014 subseries is used. figure 8-27 shows an example of connection to use the sbi mode, and figure 8-28 shows the communication format. figure 8-27. example of connection in sbi mode pd78014 master sck0 sb0 sck0 sb0 slave cpu sck sb v dd slave cpu sck sb m pd78014 slave m
214 chapter 8 applications of serial interface figure 8-28. communication format in sbi mode (a) address transmission (b) command transmission (c) data transmission/reception table 8-5. signals in sbi mode signal name output by: meaning address master selects slave device command master command to slave device data master/slave data to be processed by slave or master clock master serial data transmission/reception synchronization signal ack receiver side note reception acknowledge signal busy slave busy status note this signal is output by the receiver side during normal operation. however, it is output by the master cpu in case of an error such as time out. sck0 sb0 a7 a6 a5 a4 a3 a2 a1 a0 sets reld sets cmdd sck0 sb0 c7 c6 c5 c4 c3 c2 c1 c0 sets cmdd sck0 sb0 d7 d6 d5 d4 d3 d2 d1 d0 ack sets ackd
215 chapter 8 applications of serial interface 8.3.1 application as master cpu when the m pd78014 subseries is used as a master cpu, it performs processing (a) through (d) below with respect to slave cpus. (a) address transmission (b) command transmission (c) data transmission (d) data reception while the above processing is performed, errors <1> and <2> below are checked. <1> time out processing if the master cpu transmits data and a slave does not return the ack signal within a specific time (in this example, before the watch interrupt request occurs five times), the master judges that an error has occurred. the master cpu then outputs an ack signal and terminates the processing. figure 8-29. ack signal in case of time out <2> testing bus line the master cpu tests whether data has been correctly output to the bus line by setting the transmit data to the serial i/o shift register 0 (sio0) and the slave address register (sva). because the data on the bus line is received by sio0, it confirms that the data has been output normally by testing bit 6 (coi) of the serial operating mode register 0 (csim0) (that is set when sio0 coincides with sva) at the end of transfer. figure 8-30. testing bus line in figure 8-30, the values of sio0 and sva do not coincide (sio0 = 07h and sva = 0fh). consequently, coi = 0, and an error has occurred on the bus line. sio0 = 0fh 0 0 0 01111 sb0 = 07h 0 0 0 00111 1 sb0 ack end of transfer inttm3 ( ackd test ) (time out) master output
216 chapter 8 applications of serial interface (1) description of package m_trans : master sbi transfer subroutine name tr_mode : storage area of transfer mode select value trndat : transmit data storage area rcvdat : receive data storage area tradr : address transmit mode select value trcmd : command transmit mode select value trdat : data transmit mode select value rcdat : data reception mode select value errorf : error status test flag subroutine a name usage attribute bytes tr_mode stores transfer mode select value saddr 1 ackct time out counter trndat stores transmit data rcvdat stores receive data name usage rcvflg sets reception mode busyfg sets busy status errorf sets error status ackwfg sets ack signal wait status 2 levels 5 bytes ? serial interface channel 0 ? watch timer ? sets serial interface channel 0 selects sbi mode and sb1 pin csim0=#10010011b ? serial clock: f xx /2 5 tcl3=# 1001b ? makes so0 latch high relt=1 ? makes p27 output latch high p27=1 ? watch timer interval: 1.95 ms tmc2=#00100110b ? enables watch timer interrupt
217 chapter 8 applications of serial interface set the transfer mode and necessary data, and call m_trans. when execution has returned from the subroutine, occurrence of a transfer error can be checked by testing the error flag (errorf). in the reception mode, the receive data is stored to rcvdat after execution has returned from the subroutine. (2) example of use extrn m_trans,tr_mode,tradr,trcmd,trdat,rcdat extrn trndat,rcvdat extbit errorf sck0 equ p2.7 sb1 equ p2.5 set1 sb1 csim0=#10010111b tcl3=#10011001b tmc2=#00100110b clr1 bsye set1 relt set1 sck0 clr1 sb1 clr1 csimk0 clr1 tmmk3 ei tr_mode=#tradr trndat=#5ah call !m_trans if_bit(errorf) error processing endif . . . . . . . . ; operates in sbi mode ; sck0 = 262 khz ; sets interval of watch timer to 1.95 ms ; disables output of busy signal ; sets output latch ; enables serial interface channel 0 interrupt ; enables watch timer interrupt ; enables master interrupt sets transfer mode sets transmit data calls m_trans if: error occurs error processing
218 chapter 8 applications of serial interface (3) spd chart m_trans case: tr_mode outputs command signal of: tradr while: sb0 = low while: sck0 = low outputs bus release signal of: trcmd outputs command signal while: sb0 = low while: sck0 = low of: trdat sets transmission mode clears rcvflg break of: rcdat sets reception mode sets rcvflg sets output off data (ffh) of bus line break sets transmission status sets busyfg sets transmit data to sio0 and sva while: transfer in progress (sets busyfg) stores data of sio0 to rcvdat if: transmission mode if: error occurs in bus line sets error status sets errorf then then
219 chapter 8 applications of serial interface intcsi0 selects register bank 0 if: transmission mode if: ack signal not received then then sets ack wait status sets ackwfg else clears busy status clears error status clears busyfg clears errorf outputs ack signal else clears busyfg and errorf inttm3 selects register bank 0 if: ack wait status then if: ack received then if: time out clears ack wait status clears ackwfg clears busy status clears busyfg else time out error processing clears ack wait status clears ackwfg clears busy status clears busyfg then
220 chapter 8 applications of serial interface (4) program list public m_trans,tr_mode,tradr,trcmd,trdat,rcdat public trndat,rcvdat,errorf vecsi0 cseg at 0eh dw intcsi0 vetm3 cseg at 12h dw inttm3 sbi_dat dseg saddr trndat: ds 1 rcvdat: ds 1 tr_mode:ds 1 ackct: ds 1 sbi_flg bseg rcvflg dbit busyfg dbit errorf dbit ackwfg dbit sb0 equ p2.5 sck0 equ p2.7 tradr equ 1 trcmd equ 2 trdat equ 3 rcdat equ 4 ; sets vector address of serial interface channel 0 ; sets vector address of watch timer ; transmit data ; receive data ; sets transfer mode ; ack time out count ; sets reception mode ; transfer status ; error display ; ack wait status ; selects address transmission mode ; selects command transmission mode ; selects data transmission mode ; selects data reception mode
221 chapter 8 applications of serial interface ;******************************************* ;* sbi data transfer processing ;******************************************* sbi_seg cseg m_trans: switch(tr_mode) case tradr: set1 pm2.5 while_bit(!sb0) clr1 pm2.5 endw while_bit(!sck0) endw set1 cmdt nop set1 relt a=#trcmd case trcmd: set1 pm2.5 while_bit(!sb0) clr1 pm2.5 endw while_bit(!sck0) endw set1 cmdt a=#trdat case trdat: clr1 rcvflg a=trndat break case rcdat: set1 rcvflg mov a,#0ffh break ends set1 busyfg sva=a sio0=a while_bit(busyfg) endw rcvdat=sio0 (a) if_bit(!rcvflg) if_bit(!coi) set1 errorf endif endif ret ; sb0 = high? ; sck = high? ; outputs command signal ; wait ; outputs bus release signal ; sb0 = high? ; sck = high? ; outputs command signal ; sets transmission mode ; sets transmit data ; sets reception mode ; turns off receive buffer ; sets transfer status ; tests bus line ; starts transfer ; transfer in progress ; stores receive data ; transmission mode ; bus line output abnormal ; sets error status
222 chapter 8 applications of serial interface ; transmission mode ; acknowledge signal not received ; sets acknowledge signal wait status ; clears busy status ; clears error status ; outputs acknowledge signal ; clears busy status ; clears error status ; acknowledge signal wait status? ; acknowledge signal received? ; clears acknowledge signal wait status ; clears busy status ; time out? ; time out error processing ; clears acknowledge signal wait status ; clears busy status ;*************************************** ;* intcsi0 interrupt processing ;*************************************** csi_seg cseg intcsi0: sel rb0 if_bit(!rcvflg) if_bit(!ackd) ackct=#5 set1 ackwfg else clr1 busyfg clr1 errorf endif else set1 ackt clr1 busyfg clr1 errorf endif ret ;*************************************** ;* time out processing ;*************************************** tm3_seg cseg inttm3: sel rb0 if_bit(ackwfg) if_bit(ackd) clr1 ackwfg clr1 busyfg else ackct-- if(ackct==#0) set1 ackt set1 errorf clr1 ackwfg clr1 busyfg endif endif endif
223 chapter 8 applications of serial interface 8.3.2 application as slave cpu a slave cpu receives addresses, commands, and data from the master cpu and transmits data to the master cpu. in the example shown in this section, addresses are received by using the wake-up function. this function is to generate an interrupt only when the address value transmitted by the master to the slave coincides with the value set to the slave address register (sva) of the slave in the sbi mode. therefore, only the slave cpu selected by the master cpu generates intcsi0, and the slave cpus not selected operates without generating an inadvertent interrupt request. the slave cpu clears the wake-up function when it has been selected by the master (the interrupt request signal is generated at the end of transmission), and interfaces with the master cpu. addresses, commands, and data being transmitted are identified by using reld and cmdd (bits 2, 3 of serial bus interface control register (sbic)) of the serial bus interface control register (sb ic). because the slave cpu is not automatically placed in the unselect status, a program that returns the slave cpu to the unselect status must be prepared by processing commands between the master and cpu. (1) description of package rcvdat: receive data storage area bank 0: a name usage attribute bytes rcvdat stores receive data saddr 1 name usage rcvflg sets reception mode 1 level 3 bytes ? serial interface channel 0 ? setting of serial interface channel 0 sets sbi mode, sbi pin, and wake-up mode, csim0=#10010011b and inputs serial clock from external source ? outputs synchronous busy signal byse=1 ? makes so0 latch high relt=1 ? slave address sva=#slvadr ? enables serial interface channel 0 interrupt
224 chapter 8 applications of serial interface the interrupt processing is started by generation of intcsi0. the interrupt processing performs the following processing: ? identifies address/command/data ? outputs ack signal ? stores receive data to rcvdat (2) example of use extrn rcvdat extbit rcvflg slvadr equ 5ah sb1 equ p2.5 set1 sb1 csim0=#10110100b set1 relt set1 bsye sva=#slvadr sio0=#0ffh clr1 sb1 clr1 csimk0 ei (3) spd chart . . . . ; inputs external clock, sets sb1 pin, and selects wake-up mode ; sets output latch to high level ; sets busy automatic output ; sets slave address ; serial transfer start command ; enables serial interface channel 0 interrupt ; enables master interrupt intcsi0 selects register bank 0 then if: address received clears wake-up mode outputs ack signal address coincidence processing else if: command received then command reception processing outputs ack signal else if: reception mode then data reception processing outputs ack signal else data transmission processing stores sio0 data to memor y
225 chapter 8 applications of serial interface (4) program list vecsi0 cseg at 0eh dw intcsi0 sci_dat dseg saddr rcvdat: ds 1 csi_flg bseg rcvflg dbit csi_seg cseg ;*************************************** ;* intcsi0 interrupt processing ;*************************************** intcsi0: sel rb0 if_bit(reld) clr1 wup set1 ackt ; user processing (address reception) ;*************************************** elseif_bit(cmdd) ; user processing (command reception) set1 ackt else if_bit(rcvflg) ; user processing (data reception processing) set1 ackt else ; user processing (data transmission processing) endif ;*************************************** endif rcvdat=sio0 (a) reti ; sets vector address of serial interface channel 0 ; receive data storage area ; sets reception mode ; to address reception ; clears wake-up mode ; outputs acknowledge signal ; to command reception ; outputs acknowledge signal ; outputs acknowledge signal
226 chapter 8 applications of serial interface 8.4 interface in 3-wire serial i/o mode in this section, examples of communication between the master and a slave by using the 3-wire serial i/o mode (serial clock, data input, data output) of the serial channel 0 of the 78k/0 series are shown. in these examples, one extra busy signal is used as a handshake signal for simultaneous transmission/reception between the master and slave. this busy signal is active-low and is output by the slave. the data is 8 bits long and transmitted with the msb first. in the examples in this section, the m pd78014 subseries is used. figure 8-31. example of connection in 3-wire serial i/o mode figure 8-32. communication format in 3-wire serial i/o mode master sck0 sck0 slave si0 so0 so0 si0 busy busy busy sck0 so0 si0 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0
227 chapter 8 applications of serial interface 8.4.1 application as master cpu the serial clock is set to f x /2 5 , and communication is executed in synchronization with this serial clock between the master and slave cpus. the master cpu starts transmission after it has set the transmit data. if the slave cpu is busy (when the busy signal is low), however, the master does not transmit data and sets the busy flag (busyfg). (1) description of package trans : name of 3-wire transfer subroutine of master tdata : transmit data storage area rdata : receive data storage area busy : busy signal input port trend : transfer end test flag busyfg : busy status test flag interrupt : bank 0, a subroutine : a name usage attribute bytes tdata stores transmit data saddr 1 rdata stores receive data name usage trend sets transfer end status busyfg sets busy status 2 levels 5 bytes ? serial interface channel 0 ? p33 ? setting of serial interface channel 0 3-wire serial i/o mode, msb first csim0=#10000011b ? serial clock f x /2 5 tcl3=# 1001b ? makes p27 output latch high p27=1 ? p33 input mode ? enables serial interface channel 0 interrupt
228 chapter 8 applications of serial interface set the transmit data to tdata and call trans. after execution has returned from the subroutine, test the busy flag (busyfg). if the busy flag is set, transfer has not been executed and therefore, you must execute it again. if the busy flag is cleared, transfer has ended and the receive data has been stored to rdata. (2) example of use extrn tdata,rdata,trans extbit trend,busyfg,busy sck0 equ p2.7 csim0=#10000011b tcl3=#10011001b set1 sck0 set1 pm3.3 clr1 csimk0 ei tdata=a repeat clr1 busyfg call !trans until_bit(!busyfg) while_bit(!trend) endw a=rdata . . . . . . . . ; sets 3-wire serial i/o mode with msb first ; sets sck0 = 262 khz ; sets p3.3 input mode ; enables serial interface channel 0 ; sets transmit data ; busy test ; ends transfer ; loads receive data sets transmit data until: busyfg cleared clears busyfg calls trans while: trend cleared loads receive data
229 chapter 8 applications of serial interface (3) spd chart (4) program list public trans,rdata,tdata,busy,trend,busyfg vecsi0 cseg at 0eh dw intcsi0 busy equ 0ff03h.3 csi_dat dseg saddr rdata: ds 1 tdata: ds 1 csi_flg bseg trend dbit busyfg dbit csi_seg cseg ;************************************** ;:* intcsi0 interrupt processing ;************************************** intcsi0: sel rb0 rdata=sio0 (a) set1 trend reti ;************************************** ;* 3-wire (master) ;************************************** trans: if_bit(busy) sio0=tdata (a) else set1 busyfg endif ret ; sets vector address of serial interface channel 0 ; 0ff03h = port3 ; receive data storage area ; transmit data storage area ; sets transfer end status ; sets busy status ; stores receive data ; sets transfer end status ; enables transfer ; sets transmit data ; sets busy status trans if: transfer enabled sets transmit data to sio0 then else sets busy status sets busyfg intcsi0 selects register bank 0 stores data of sio0 to memory sets transfer end status sets trend
230 chapter 8 applications of serial interface 8.4.2 application as slave cpu in this example, a slave cpu simultaneously transmits and receives 8-bit data in synchronization with the serial clock from the master cpu. the busy signal output by the slave cpu is low (busy status) while the transmit data is prepared. this busy signal is cleared (high level) when the transmit data is set (call !trans), and is output (low level) when interrupt intcsi0 occurs at the end of transfer. therefore, the busy status remains after the end of transfer until the data is set. figure 8-33. output of busy signal (1) description of package trans : name of 3-wire transfer subroutine of slave tdata : transmit data storage area rdata : receive data storage area busy : busy signal output port trend : transfer end test flag interrupt : bank 0, a subroutine : a name usage attribute bytes tdata stores transmit data saddr 1 rdata stores receive data name usage trend sets transfer end status 2 level 5 bytes ? serial interface channel 0 ? p33 busy waits for transmission transmission in progress transmit data being prepared sets transmit data intcsi0 sets transmit data
231 chapter 8 applications of serial interface ? setting of serial interface channel 0 sets 3-wire serial i/o mode with msb first, and inputs external clock csim0=#10000000b ? p33 output mode p33=0 ? setting of busy status ? enables serial interface channel 0 set the transmit data to tdata and call trans. because the busy signal is cleared by the processing of trans, the slave waits for communication with the master. after the communication has ended, intcsi0 occurs and interrupt processing is started. you can check the end of transfer by testing trend. after trend has been set, the receive data has been stored to rdta. (2) example of use extrn tdata,rdata,trans extbit trend,busy csim0=#10000000b clr1 busy clr1 pm3.3 clr1 csimk0 ei tdata=a call !trans while_bit(!trend) endw a=rdata ; sets 3-wire i/o mode with msb first ; busy status ; p3.3 output mode ; enables serial interface channel 0 ; sets transmit data ; ends transfer ; loads receive data . . . . . . . . sets transmit data calls trans while: trend cleared loads receive data
232 chapter 8 applications of serial interface (3) spd chart (4) program list public rdata,tdata,busy,trend,busyfg public trans vecsi0 cseg at 0eh dw intcsi0 csi_dat dseg saddr rdata: ds 1 trada: ds 1 csi_flg bseg trend dbit busyfg dbit busy equ 0ff03h.3 csi_seg cse ;************************************** ;* intcsi0 interrupt processing ;************************************** intcsi0: sel rb0 clr1 busy rdata=si00 (a) set1 trend reti ;************************************** ;* 3-wire (slave) ;************************************** trans: sio0=tdata (a) set1 busy ret ; sets vector address of serial interface channel 0 ; stores receive data ; stores transmit data ; sets transfer end status ; sets busy status ; 0ff03h = port3 ; sets busy status ; stores receive data ; sets transfer end status ; sets transmit data ; clears busy status trans sets transmit data to sio0 clears busy signal intcsi0 selects register bank 0 outputs busy signal stores sio0 data to memory sets transfer end status
233 chapter 8 applications of serial interface 8.5 half-duplex start-stop synchronization communication half-duplex start-stop synchronization communication can be executed by using clocked serial interface channel 0. the three-wire serial i/o mode and sbi mode may be used. in this example, the m pd78014 subseries is used. the communication protocol is as follows: transfer rate : 9600 bps start bit : 1 bit character length : 8 bits (lsb first) parity bit : 1 bit (even or odd parity selectable) stop bit : 2 bits the serial clock is generated by using 8-bit timer/event counter 2 because the transfer rate is set to 9600 bps. 8.5.1 half-duplex start-stop synchronization communication in 3-wire serial i/o mode figure 8-34 shows the system configuration. serial data are input to the si0 pin and output from the so0 pin. bits 0 and 1 of port 3 are used to input and output the busy signal. when the busy signal is l, serial communication is enabled. figure 8-34. system configuration (in 3-wire serial i/o mode) intp1 si0 so0 p30 p31 so0 si0 intp1 p31 p30 serial i/o busy signal i/o pd78014 pd78014 m m
234 chapter 8 applications of serial interface (1) transmission in 3-wire serial i/o mode data are transmitted as follows: <1> start bit ? wait for transmission time by manipulating the output latch of the serial interface and by using 8-bit timer/event counter 2. caution to prevent data reception timing from being delayed because of missing of the start bit, increase the priority of intp1 interrupt request. <2> data ? transmitted by serial buffer. <3> parity bit ? output the parity bit by manipulating the output latch of the serial interface through interrupt processing of 8-bit timer/even counter 2. caution to prevent transmission timing from being delayed, increase the priority of the 8-bit timer/event counter 2 interrupt request. <4> stop bit ? set the output latch of the serial interface through interrupt servicing of 8-bit timer/event counter 2 and output the stop bit. caution to prevent transmission timing from being delayed, increase the priority of the 8-bit timer/ event counter 2 interrupt request. figure 8-35. transmission format in 3-wire serial i/o mode serial busy input pin p30 serial data output so0 serial clock timer 2 interrupt request output by receiver side start bit d1 d0 d2 d3 d4 d5 d6 d7 parity bit stop bit timer 2 starts operatin g . writes data to sio0. enables intcsi0 and timer 2 interrupts. disables timer 2 interrupt. processing
235 chapter 8 applications of serial interface (2) reception in 3-wire serial i/o mode data are received as follows: <1> start bit ? reception is started by detecting the falling of the intp1 pin and through port test. caution to prevent data reception timing from being delayed because of missing of the start bit, increase the priority of intp1 interrupt request. <2> data ? received by serial buffer. <3> parity bit ? output the parity bit by testing the port with the interrupt processing of 8-bit timer/event counter 2. caution to prevent reception timing from being delayed, increase the priority of the 8-bit timer/ event counter 2 interrupt request. <4> stop bit ? output the stop bit by testing the port with the interrupt servicing of 8-bit timer/event counter 2. caution to prevent reception timing from being delayed, increase the priority of the 8-bit timer/ event counter 2 interrupt request. if a parity error or overrun error occurs, the flag is set. figure 8-36. reception format in 3-wire serial i/o mode serial busy input pin p31 serial data input si0 serial clock timer 2 interrupt request inverted by serial interrupt start bit d1 d0 d2 d3 d4 d5 d6 d7 parity bit stop bit intp1 interrupt. timer 2 starts operating. writes ffh to sio0. disables intp1. enables intcsi0 interrupt and timer 2 interrupts. timer 2 interrupt processing disables timer 2 interrupt.
236 chapter 8 applications of serial interface (3) description of package ? subroutine name s_soshin : subroutine for transmission s_jushin : subroutine for reception ? input parameters sodata : stores transmit data. f_parity : indicates selected even or odd parity. f_tushin : indicates reception or transmission in progress. ? output parameters judata : stores receive data. f_data : set when reception is completed. f_errp : indicates error of parity. f_erre : indicates error of end bit ? i/o parameters f_padata : stores transmitted/received parity bit. bank 0 a bank 1 a bank 2 a name usage attribute bytes sodata transmit data storage area saddr 1 judata receive data storage area saddr 1 c_work status storage counter saddr 1 i loop processing work counter saddr 1 j loop processing work counter saddr 1 name usage f_parity parity select flag set when odd parity is selected f_padata parity bit storage flag stores parity. f_tushin communication flag set during communication. f_errp parity error flag set in case of parity error. f_erre end bit error flag set in case of end bit error. f_data reception completion flag set on completion of reception. f_work work flag for work
237 chapter 8 applications of serial interface 1 level 3 bytes ? serial interface channel 0 (3-wire serial i/o mode) ? 8-bit timer/event counter 2 ? external interrupt edge detection (intp1 pin) ? set by subroutines s_soshin and s_jushin. ? port 2: 5-bit input port, 6-bit output port pm2 = # 01 b ? port 3: 0-bit input port, 1-bit output port pm3 = # 01b ? setting of serial interface channel 0 3-wire serial i/o mode, serial clock = selected by 8-bit timer/event counter 2 csim0 = #10000110b ? setting of 8-bit timer/event counter 2 baud rate: 9600 bps cr20 = #54 8-bit timer register 2 channels mode tcl1 = #01110000b 8-bit timer/event counter 2 disabled toc1 = #0000000b tmc1 = #0000000b ? setting of intp1: falling edge of intp1 intm0 = #0000000b ? 8-bit timer/event counter 2 interrupt priority: high clr1 tmpr2 ? intp1 interrupt priority: high clr1 ppr1 ? serial interface interrupt enabled clr1 csimk0 ? start data transmission and reception in the following sequence: ? starting data transmission <1> store the transmit data to the sodata area. <2> set the transmit flag. <3> call subroutine s_soshin. ? starting data reception <1> clear the communication flag (f_tushin) to 0. <2> invert the busy signal. <3> call subroutine s_jushin. ? when using an interrupt request other than those of the 78k/0 series package, clear the isp flag to 0 before interrupt servicing to enable the interrupt request in order to enable a high-priority interrupt.
238 chapter 8 applications of serial interface (4) example here is an example of selecting odd or even parity bit, and transmission or reception through key input. extrn sodata extrn judata,s_soshin,s_jushin extbit f_parity,f_data,f_padata,f_tushin extbit f_erre,f_errp ; busy_0 equ p3.1 busy_1 equ p3.0 parikey equ 22 jyushin equ 21 tushin equ 20 ;************************************************ ; initialize ;************************************************ veres cseg at 00h dw res_sta m3 cseg res_sta: mov p2,#0bfh mov p3,#0ffh mov pm2,#00100000b mov pm3,#00000001b ;***setting of 8-bit timer register*** cr20=#54 tcl1=#01110000b toc1=#00000000b tmc1=#00000000b ;***setting of serial interface 0*** csim0=#10000110b set1 relt ;***setting of intp1*** intm0=#00000000b clr1 tmpr2 clr1 ppr1 clr1 pif1 clr1 tmif2 clr1 csiif0 clr1 csimk0 while(forever) ; decoded value of parity key ; decoded value of reception key ; decoded value of transmission key ; ; ; p2.5 = h, p2.6 = l ; ; p2.5 = input port, p2.6 = output port ; p3.0 = input port, p3.1 = output port ; ; count clock: 1.05 mhz ; ; selects 8-bit timer register, disables timer 2 operation ; selects 3-wire mode, serial clock, 8-bit timer 2 ; ; intp1 falling edge ; timer 2 interrupt high priority ; intp1 interrupt high priority ; clears intp1 request flag ; clears timer 2 interrupt request flag ; clears serial interface interrupt flag ; enables serial interface interrupt ; ;
239 chapter 8 applications of serial interface if_bit(f_keyon) switch(m_keyon) case parikey: set1 cy cy ^= f_parity f_parity=cy break case tushin: set1 f_tushin clr1 f_soend break case jyushin: clr1 f_tushin cy=busy_0 not1 cy busy_0=cy if_bit(cy) set1 pmk1 else clr1 f_errp clr1 f_erre call !s_jushin endif break ends endif ? ? ? if_bit(!f_soend) if_bit(f_tushin) cy=busy_i if_bit(!cy) sodata=#0 set1 f_soend sodata=work call !s_soshin endif endif endif ; key on flag 1? ; ; parity key is pressed. ; alternately detects odd and even parities. ; ; ; ; communication key is pressed. ; sets communication flag (during transmission). ; ; ; communication key is pressed. ; clears communication flag (during reception). ; outputs inverted busy signal data. ; ; ; ; disables intp1 interrupt. ; ; ; ; ; ; ; ; ; ; communication flag set? ; busy signal non-active? ; ; ; ; transmit data storage area ? transmit data ; ; ; ;
240 chapter 8 applications of serial interface (5) spd chart [reception subroutine] [transmission subroutine] then if (odd parity selected) sets parity data flag s_soshin for (i = # 0 ; i < #8 ; i++) cy ? least significant bit of transmit data exclusive-ors cy and parity data flag transfers result to parity data flag resets timer output f/f of 8-bit timer/event counter 2 and enables inversion operation clears request flag of 8-bit timer/event counter 2 disables interrupt enables 8-bit timer/event counter 2 operation transmits start bit waits for start bit transmission time sio0 ? transmit data enables interrupt clears intp1 request flag enables intp1 interrupt s_jushin
241 chapter 8 applications of serial interface [parity end bit transmission processing (8-bit timer/event counter 2 interrupt)] selects bank 1 if (data transmission in progress) taima2 then switch (which data is transmitted?) [case : 1] [case : 2] [case : 3] transmits parity data first transmission of end bit second transmission of end bit disables 8-bit timer/event counter 2 interrupt disables 8-bit timer/event counter 2 operation switch (which data is received?) [case : 1] [case : 2] [case : 3] inputs parity data if (first end bit error?) then sets end bit error flag then sets end bit error flag if (second end bit error?) disables 8-bit timer/event counter 2 interrupt disables 8-bit timer/event counter 2 operation if (parity data ok?) then if (end bit ok?) then sets reception completion flag else sets parit y error fla g
242 chapter 8 applications of serial interface [data transmission/reception completion processing] [data reception start processing (intp1 interrupt processing)] intp1 selects bank 1 clears 8-bit timer/event counter 2 request flag clears 8-bit timer/event counter enables 8-bit timer/event counter 2 operation waits for start bit input time if (intp1 pin check ok?) then disables intp1 interrupt prepares for input of receive data intsi0 selects bank 2 clears 8-bit timer/event counter 2 request flag enables 8-bit timer/event counter 2 interrupt outputs "h" to busy0 signal if (reception in progress) then inputs receive data
243 chapter 8 applications of serial interface (6) program list public f_padata,f_parity public f_data,f_tushin public judata,sodata,s_jushin,s_soshin public f_errp,f_erre ; veintp1 cseg at 08h dw intp1 veintsi0 cseg at 0eh dw intsi0 vetim2 cseg at 18h dw taima2 ; si0 equ p2.5 busy_0 equ p3.1 busy_i equ p3.0 ; moram dseg saddr sodata: ds 1 c_work: ds 1 judata: ds 1 i: ds 1 k: ds 1 ; moflg bseg f_parity dbit f_errp dbit f_erre dbit f_data dbit f_padata dbit f_work dbit f_tushin dbit ;************************************************ ; reception routine ;************************************************ jushin cseg s_jushin: clr1 pif1 clr1 pmk1 ret ; sets vector address of intp1 ; sets vector address of serial interface channel 0 ; sets vector address of 8-bit timer 2 ; transmit data storage area ; work counter ; receive data storage area ; work counter ; work counter ; parity select flag ; parity error flag ; end bit error flag ; reception completion flag ; parity data flag ; work flag ; communication flag ; ; ; clears intp1 request flag ; enables intp1 interrupt ;
244 chapter 8 applications of serial interface ;************************************************ ; transmission routine ;************************************************ soshin cseg s_soshin: clr1 f_padata if_bit(f_parity) set1 f_padata endif a=sodata for(i=#0;i<#8;i++) rorc a,1 cy ^= f_padata f_padata = cy next toc1=#01100000b (a) clr1 tmif2 di set1 tce2 set1 cmdt while_bit(!tmif2) endw clr1 tmif2 sio0=sodata (a) ei ret ;************************************************ ; timer 2 interrupt processing ;************************************************ tim2 cseg taima2: sel rb1 if_bit(f_tushin) if(c_work <= #4) switch(c_work) case 0: if_bit(f_padata) set1 relt else set1 cmdt endif break case 2: set1 relt break case 4: set1 relt set1 tmmk2 clr1 tce2 c_work=#0 break ends c_work++ else c_work=#0 endif ; ; clears parity data flag ; odd parity selected? ; sets parity data ; ; ; determines parity data ; ; ; ; ; ; clears timer 2 request flag ; ; enables 8-bit timer operation ; transmits start bit ; waits for start bit transmission time ; ; ; starts data transmission ; ; ; ; ; sets bank 1 ; communication flag set? ; contents of work counter ; 0: transmits parity data ; ; ; ; ; ; ; ; 2: transmits end bit ; transmits h ; ; 4: transmits end bit ; transmits h ; disables timer 2 interrupt ; disables 8-bit timer operation ; ; ; ; ; ; ;
245 chapter 8 applications of serial interface else if(c_work <= #6) switch(c_work) case 1: cy=si0 f_padata=cy break case 3: if_bit(!si0) set1 f_erre endif break case 5: if_bit(!si0) set1 f_erre endif c_work=#0 set1 tmmk2 clr1 tce2 clr1 f_work if_bit(f_parity) set1 f_work endif a=judata for(i=#0;i<#8;i++) rorc a,1 cy ^= f_work f_work = cy next clr1 f_errp clr1 f_data f_work ^= f_padata (cy) if_bit(!f_work) if_bit(!f_erre) set1 f_data endif else set1 f_errp endif break ends c_work++ else c_work=#0 endif endif reti ; ; reception in progress? ; contents of work counter ; 1: inputs parity data ; ; ; ; 3: checks end bit ; if error, sets end bit error flag ; ; ; ; 5: checks end bit ; if error, sets end bit error flag ; ; ; ; disables timer 2 interrupt ; disables 8-bit timer operation ; ; ; ; ; ; adds receive data ; ; ; ; ; ; ; ; checks parity bit ; checks end bit data ; ; ; sets f_data if parity data is ok ; sets parity error flag if parity data is not ok ; ; ; ; ; ; ; ; ;
246 chapter 8 applications of serial interface ;************************************************ ; intsi0 interrupt processing (reception) ;************************************************ s_si0 cseg intsi0: sel rb2 clr1 tmif2 clr1 tmmk2 set1 busy_o if_bit(!f_tushin) judata=sio0 (a) endif c_work=#0 reti ;************************************************ ; intp1 interrupt processing (reception) ;************************************************ s_p1 cseg intp1: sel rb1 clr1 tmif2 clr1 tce2 set1 tce2 while_bit(!tmif2) endw clr1 tmif2 if_bit(!si0) toc1=#10100000b set1 pmk1 si00=#0ffh endif reti end ; ; ; sets bank 2 ; clears timer 2 request flag ; enables timer 2 interrupt ; outputs busy signal h ; ; ; ; clears work counter to zero ; ; ; ; ; clears timer 2 request flag ; clears timer 2 counter ; enables timer operation ; ; ; ; chattering processing of intp1 ; ; disables intp1 interrupt ; ; ;
247 chapter 8 applications of serial interface 8.5.2 half-duplex start-stop synchronization communication in sbi mode figure 8-37 shows the system configuration. serial data is input or output to or from the sb0 pin. bits 0 and 1 of port 3 are used to input or output the busy signal. serial communication is enabled when the busy signal is l. note the following points when using the sbi mode. <1> set the fifth bit (sb0) of port 2 in the output mode on resetting and restarting. to test sb0, however, set sb0 in the input mode. after testing, set sb0 in the output mode again. <2> after transmission and detection of the last stop bit for serial transmission/reception have been completed, disable the serial operation, and then enable it again. usually, the end of sbi communication is detected by checking the ready signal after the acknowledge signal has been output. because the acknowledge signal is used to transmit or receive the parity bit in this example, however, the sbi communication end condition is not satisfied if parity bit 1 is transmitted or received. if the end of serial communication is not detected, the next communication may not be performed correctly. figure 8-37. system configuration (sbi mode) sb0 intp1 p30 p31 sb0 intp1 p31 p30 serial i/o busy signal i/o pd78014 pd78014 mm
248 chapter 8 applications of serial interface (1) transmission in sbi mode data are transmitted as follows: <1> start bit ? wait for transmission time by manipulating the output latch of the serial interface and by using 8-bit timer/event counter 2. caution to prevent data reception timing from being delayed because of missing of the start bit, increase the priority of intp1 interrupt request. <2> data and parity bit ? transmit 9 bits by using the serial buffer and acknowledge signal. <3> stop bit ? set the output latch of the serial interface through interrupt servicing of 8-bit timer/event counter 2 and output the stop bit. cautions 1. to prevent transmission timing from being delayed, increase the priority of the 8- bit timer/event counter 2 interrupt request. 2. after transmission of the second stop bit has been completed, disable the serial operation and then enable it again to check the completion of transmission. figure 8-38. transmission format in sbi mode note enable the interrupt after disabling the serial operation. serial busy input pin p30 serial data output sb0 serial clock timer 2 interrupt request output by receiver side start bit d1 d0 d2 d3 d4 d5 d6 d7 parity bit stop bit timer 2 starts operating. writes parity bit to acke writes data to sio0. enables intcsi0 and timer 2 interrupts. disables timer 2 interrupt note processing
249 chapter 8 applications of serial interface (2) reception in sbi mode data are received as follows: <1> start bit ? reception is started by detecting the falling of the intp1 pin and through port test. cautions 1. test the port in the following sequence: <1> set bit 5 (si0) of port 2 in the input mode. <2> test the port. write data to sio0. <3> set bit 5 of port 2 in the output mode again. 2. to prevent data reception timing from being delayed because of missing of the start bit, increase the priority of intp1 interrupt request. <2> data and parity bit ? reception by serial buffer and acknowledge detection <3> stop bit ? test the port by 8-bit timer/event counter 2 interrupt servicing and output the parity bit. cautions 1. to prevent transmission timing from being delayed, increase the priority of the 8-bit timer/ event counter 2 interrupt request. 2. after transmission of the second stop bit has been completed, disable the serial operation and then enable it again to check the completion of transmission. if a parity error or overrun error occurs, the flag is set. figure 8-39. reception format in sbi mode serial busy output pin p31 serial data input sb0 serial clock timer 2 interrupt request inverted by serial interrupt start bit d1 d0 d2 d3 d4 d5 d6 d7 stop bit intp1 interrupt. timer 2 starts operating. writes ffh to sio0. disables intp1. enables intcsi0 interrupt and timer 2 interrupts. timer 2 interrupt processing disables timer 2 interrupt. parity bit
250 chapter 8 applications of serial interface (3) description of package ? subroutine name s_soshin : subroutine for transmission s_jushin : subroutine for reception ? input parameters sodata : stores transmit data. f_parity : indicates selected even or odd parity. f_tushin : indicates reception or transmission in progress. ? output parameters judata : stores receive data. f_data : set when reception is completed. f_errp : indicates error of parity. f_erre : indicates error of end bit ? i/o parameters f_padata : stores transmitted/received parity bit. bank 0 a bank 1 a bank 2 a name usage attribute bytes sodata transmit data storage area saddr 1 judata receive data storage area saddr 1 c_work status storage counter saddr 1 i loop processing work counter saddr 1 j loop processing work counter saddr 1 name usage f_parity parity select flag set when odd parity is selected f_padata parity bit storage flag stores parity. f_tushin communication flag set during communication. f_errp parity error flag set in case of parity error. f_erre end bit error flag set in case of end bit error. f_data reception completion flag set on completion of reception. f_work work flag for work
251 chapter 8 applications of serial interface 1 level 3 bytes ? serial interface channel 0 (sbi mode) ? 8-bit timer/event counter 2 ? external interrupt edge detection (intp1 pin) ? set the pin used to input/output data (p25) as follows after resetting and restarting, and before serial transfer of the first byte: <1> set the output latch of p25 to 1. <2> set bit 0 (relt) of the serial bus control register (sbic) to 1. <3> clear the output latch of p25, which has been set to 1, to 0. ? set by subroutines s_soshin and s_jushin. ? port 2: 5-bit input port, 6-bit output port pm2 = # 01 b ? port 3: 0-bit input port, 1-bit output port pm3 = # 01b ? setting of serial interface channel 0 sbi mode, serial clock = selected by 8-bit timer/event counter 2 csim0 = #10010110b ? setting of 8-bit timer/event counter 2 baud rate: 9600 bps cr20 = #54 8-bit timer register 2 channels mode tcl1 = #01110000b 8-bit timer/event counter 2 disabled toc1 = #00000000b tmc1 = #00000000b ? setting of intp1: falling edge of intp1 intm0 = #00000000b ? 8-bit timer/event counter 2 interrupt priority: high clr1 tmpr2 ? intp1 interrupt priority: high clr1 ppr1 ? serial interface interrupt enabled clr1 csimk0 ? start data transmission and reception in the following sequence: ? starting data transmission <1> store the transmit data to the sodata area. <2> set the transmit flag. <3> call subroutine s_soshin. ? starting data reception <1> clear the communication flag (f_tushin) to 0. <2> invert the busy signal. <3> call subroutine s_jushin. ? when using an interrupt request other than those of the 78k/0 series package, clear the isp flag to 0 before interrupt servicing to enable the interrupt request in order to enable a high-priority interrupt.
252 chapter 8 applications of serial interface (4) example here is an example showing how to select an even or odd parity bit, and transmission or reception through key input. extrn sodata extrn judata,s_soshin,s_jushin extbit f_padata,f_parity,f_data,f_tushin extbit f_errp,f_erre ; tushin equ 20 jyushin equ 21 parikey equ 22 busy_o equ p3.1 busy_i equ p3.0 sb0 equ p2.5 ;************************************************ ; initialize ;************************************************ m3s cseg res_sta: mov p2,#9fh mov p3,#0ffh mov pm2,#00000000b mov pm3,#00000001b ;***setting of 8-bit timer register*** cr20=#54 tcl1=#01110000b toc1=#00000000b tmc1=#00000000b ;***setting of serial interface 0*** set1 sb0 csim0=#10000110b set1 relt clr1 sb0 ;***setting of intp1*** clr1 tmpr2 clr1 ppr1 intm0=#00000000b clr1 pif1 clr1 tmif2 clr1 csiif0 clr1 ksif clr1 csimk0 clr1 ksmk ; ; ; ; p2.5=h, p2.6=l ; ; p2.5 = output mode ; p3.0 = input mode, p3.1 = output mode ; ; count clock: 1.05 mhz ; ; selects 8-bit timer register and disables timer 2 operation ; ; selects sbi mode, serial clock, and 8-bit timer 2 ; ; ; increases priority of timer 2 interrupt ; increases priority of intp1 interrupt ; falling edge of intp1 ; clears intp1 request flag ; clears timer 2 request flag ; clears serial interface request flag ; clears interrupt request flag ; enables serial interface interrupt ; enables intks interrupt
253 chapter 8 applications of serial interface while(forever) ? ? if_bit(f_keyon) switch(m_keyon) case parikey: set1 cy cy ^= f_parity f_parity=cy break case tushin: set1 f_tushin clr1 f_soend break case jyushin: clr1 f_tushin cy=busy_o not1 cy busy_o=cy if_bit(cy) set1 pmk1 else clr1 f_errp clr1 f_erre call !s_jushin endif break ends endif ? ? ? if_bit(!f_soend) if_bit(f_tushin) cy=busy_i if_bit(!cy) set1 f_soend sodata=#0 sodata=work (a) call !s_soshin endif endif endif ; ; ; ; key on flag 1? ; ; parity key is pressed. ; alternately detects odd and even parities. ; ; ; ; communication key is pressed. ; clears communication flag (during transmission). ; ; ; reception key is pressed. ; clears communication flag (during reception) ; outputs inverted busy signal data. ; ; ; ; disables intp1 interrupt. ; ; ; ; ; ; ; ; communication flag set? ; busy signal non-active? ; ; ; ; ; transmit data storage area ? transmit data ; calls transmission routine ; ; ;
254 chapter 8 applications of serial interface (5) spd chart [reception subroutine] [transmission subroutine] clears intp1 request flag enables intp1 interrupt s_jushin then sets parity data flag s_soshin for (i = # 0 ; i < # 8 ; i++) cy ? least significant bit of transmit data exclusive-ors cy and parity data flag transfers result to parity data flag resets timer output f/f of 8-bit timer/event counter 2 and enables inversion operation clears request flag of 8-bit timer/event counter 2 disables interrupt enables 8-bit timer/event counter 2 operation transmits start bit waits for start bit transmission time acke ? parity bit data sio0 ? transmit data enables interrupt converts transmit data in reverse direction if (odd parity selected)
255 chapter 8 applications of serial interface [stop bit transmission/reception processing (8-bit timer/event counter 2 interrupt processing)] selects bank 1 if (data transmission in progress) taima2 then switch (which data is transmitted?) [case : 1] [case : 2] first transmission of end bit second transmission of end bit disables 8-bit timer/event counter 2 interrupt disables 8-bit timer/event counter 2 operation switch (which data is received?) [case : 1] [case : 2] if (first end bit error?) then sets end bit error flag then sets end bit error flag if (second end bit error?) disables 8-bit timer/event counter 2 interrupt disables 8-bit timer/event counter 2 operation if (parity data ok?) then sets reception completion flag else sets parity error flag
256 chapter 8 applications of serial interface [data transmission/reception completion processing (intsi0 interrupt processing)] [data reception start processing (intp1 interrupt processing)] selects bank 2 clears 8-bit timer/event counter 2 request flag enables 8-bit timer/event counter 2 interrupt outputs "h" to busy0 signal intsi0 if (reception in progress) then inputs receive data inputs receive data in reverse direction inputs parity data selects bank 1 clears 8-bit timer/event counter 2 request flag enables 8-bit timer/event counter 2 operation waits for start bit input time intp1 if (intp1 pin check ok?) then clears 8-bit timer 2 request flag disables intp1 interrupt prepares for input of receive data
257 chapter 8 applications of serial interface (6) program list public judata public sodata,f_parity,s_soshin public f_data,s_jushin,f_padata,f_tushin public f_erre,f_errp ; veintp1 cseg at 08h dw intp1 veintsi0 cseg at 0eh dw intsi0 vetim2 cseg at 18h dw taima2 ; sb0 equ p2.5 busy_o equ p3.1 busy_i equ p3.0 port25 equ pm2.5 ; mosram dseg saddr sodata: ds 1 c_work: ds 1 judata: ds 1 i: ds 1 k: ds 1 ; mosflg bseg f_errp dbit f_erre dbit f_data dbit f_padata dbit f_parity dbit f_work dbit f_tushin dbit ; ;************************************************ ; reception routine ;************************************************ jushin cseg s_jushin: clr1 pif1 clr1 pmk1 ret ; transmit data storage area ; work area ; receive data storage area ; work counter ; work counter ; parity error flag ; end bit error flag ; reception completion flag ; parity data flag ; parity select flag ; flag work area ; communication flag ; ; ; clears request flag ; enables intp1 interrupt ;
258 chapter 8 applications of serial interface ;************************************************ ; transmission routine ;************************************************ soshon cseg s_soshin: a=sodata sodata=#0 if_bit(a.7) set1 sodata.0 endif if_bit(a.6) set1 sodata.1 endif if_bit(a.5) set1 sodata.2 endif if_bit(a.4) set1 sodata.3 endif if_bit(a.3) set1 sodata.4 endif if_bit(a.2) set1 sodata.5 endif if_bit(a.1) set1 sodata.6 endif if_bit(a.0) set1 sodata.7 endif clr1 f_padata if_bit(f_parity) set1 f_padata endif a=sodata for(k=#0;k<#8;k++) rorc a.1 cy ^= f_padata f_padata = cy next toc1=#01100000b (a) clr1 tmif2 di set1 tce2 set1 cmdt while_bit(!tmif2) endw clr1 tmif2 set1 acke if_bit(f_padata) clr1 acke endif sio0=sodata (a) ei ret ; ; reverses direction of transmit data ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; clears parity data flag ; odd parity selected? ; sets parity data ; ; ; determines parity data ; ; ; ; ; ; clears timer 2 request flag ; ; enables 8-bit timer operation ; transmits start bit ; waits for start bit transmission time ; ; ; clears acknowledge ; clears acknowledge if parity data is 1 ; ; ; starts data transmission ; ;
259 chapter 8 applications of serial interface ;************************************************ ; timer 2 interrupt processing ;************************************************ tim2 cseg taima2: sel rb1 if_bit(f_tushin) if(c_work < #3) switch(c_work) case 0: set1 relt break case 2: set1 relt set1 tmmk2 clr1 tce2 set1 sb0 clr1 csie0 set1 csie0 set1 relt clr1 sb0 c_work=#0 break ends c_work++ else c_work=#0 endif ; ; ; sets bank 1 ; communication in progress? ; contents of work mode ; 0: transmits end bit ; ; ; ; 2: transmits end bit ; disables 8-bit timer 2 interrupt ; ; disables 8-bit timer 2 operation ; sets port 2.5 in input mode ; disables serial operation ; enables serial operation ; ; sets port 2.5 in output mode ; ; ; ; ; ; ;
260 chapter 8 applications of serial interface else if(c_work < #4) set1 port25 switch(c_work) case 1: if_bit(!sb0) set1 f_erre endif break case 3: if_bit(!sb0) set1 f_erre endif set1 sb0 clr1 csie0 set1 csie0 set1 relt clr1 sb0 c_work=#0 set1 tmmk2 clr1 tce2 clr1 f_work if_bit(f_parity) set1 f_work endif a=judata for(i=#0;i<#8;i++) rorc a,1 cy ^= f_work f_work = cy next clr1 f_errp clr1 f_data f_work ^= f_padata (cy) if_bit(!f_work) if_bit(!f_erre) set1 f_data endif else set1 f_errp endif clr1 f_work break ends clr1 port25 c_work++ else c_work=#0 endif endif reti ; ; reception in progress? ; sets port 2.5 in input mode. ; contents of work mode ; 1: sets end bit error flag if end bit is h ; ; ; ; ; 3: sets end bit error flag if end bit is h ; ; ; ; port 2.5 = h ; disables serial operation ; enables serial operation ; ; port 2.5 = l ; ; disables 8-bit timer 2 interrupt ; disables 8-bit timer operation ; ; ; ; ; ; adds receive data ; ; ; ; ; ; ; ; checks parity data ; ; sets f_data flag if reception is completed normally ; ; ; sets f_errp flag in case of parity error ; ; ; ; ; sets port 2.5 in output mode ; ; ; ; ; ;
261 chapter 8 applications of serial interface ; ;************************************************ ; intsi0 interrupt processing (reception) ;************************************************ s_si0 cseg intsi0: sel rb2 clr1 tmif2 clr1 tmmk2 set1 busy_o if_bit(!f_tushin) a=sio0 judata=#0 if_bit(a.7) set1 judata.0 endif if_bit(a.6) set1 judata.1 endif if_bit(a.5) set1 judata.2 endif if_bit(a.4) set1 judata.3 endif if_bit(a.3) set1 judata.4 endif if_bit(a.2) set1 judata.5 endif if_bit(a.1) set1 judata.6 endif if_bit(a.0) set1 judata.7 endif clr1 f_padata cy=ackd not1 cy f_padata=cy endif c_work=#0 reti ; ; ; ; clears timer 2 request flag ; enables timer 2 interrupt ; ; ; ; ; inputs receive data in reverse direction ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; inputs parity data ; ; ; ; ; ;
262 chapter 8 applications of serial interface ;************************************************ ; intp1 interrupt processing (reception) ;************************************************ s_p1 cseg int1: sel rb2 clr1 tmif2 clr1 tce2 set1 tce2 while_bit(!tmif2) endw clr1 tmif2 set1 port25 if_bit(!sb0) clr1 acke toc1=#10100000b st1 pmk1 sio0=#0ffh endif clr1 port25 reti end ; ; ; ; clears timer 2 request flag ; clears timer 2 counter ; enables timer operation ; ; ; ; sets port in input mode ; chattering processing of intp1 ; ; ; disables intp1 interrupt ; ; ; sets port 2.5 in output mode ;
263 chapter 9 applications of a/d converter chapter 9 applications of a/d converter the a/d converter of the 78k/0 series is a successive approximation type with an 8-bit resolution and eight channels. although only a select mode is supported as the operation mode, conversion can be started by an external trigger. if the external trigger is not used, the analog data of a selected channel is repeatedly converted into a digital signal. the a/d converter is set by the following registers: ? a/d converter mode register (adm, adm0) ? a/d converter input select register (adis) : m pd78014, 78014y, 78018f, 78018fy, 78014h subseries, m pd780001 ? analog input channel specification register (ads0) : m pd780024, 780024y, 780924 subseries caution the format of the registers provided on the m pd780024, 780024y, and 780924 subseries differs from the format of the registers used in the program examples in this chapter. when using a program example in this chapter with any of the m pd780024, 780024y, and 780924 subseries, change the setting of the registers according to the registers of the microcontroller used.
264 chapter 9 applications of a/d converter figure 9-1. format of a/d converter mode register ( m pd78014, 78014y subseries, m pd780001) adm3 adm2 adm1 selects analog input channel 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7 fr1 fr0 at f x = 10.0 mhz at f x = 8.38 mhz at f x = 4.19 mhz 0 0 160/f x setting prohibited note 2 19.1 m s 38.1 m s 0 1 80/f x setting prohibited note 2 setting prohibited note 2 19.1 m s 1 0 200/f x 20.0 m s 23.9 m s 47.7 m s 1 1 setting prohibited trg selects external trigger 0 no external trigger (software start) 1 conversion started by external trigger (hardware start) cs controls a/d conversion operation 0 stops operation 1 starts operation notes 1. set the a/d conversion time to 19.1 m s or longer. 2. these settings are prohibited because the a/d conversion time is less than 19.1 m s. cautions 1. set bit 0 to 1. 2. to reduce the power consumption of the a/d converter when the standby function is used, stop the a/d conversion operation by clearing bit 7 (cs) to 0, and then execute the halt or stop instruction. remark f x : main system clock oscillation frequency selects a/d conversion time note 1 765432 symbol 10 ff80h 1 adm adm1 adm3 adm2 fr0 fr1 trg cs address at reset r/w 01h r/w
265 chapter 9 applications of a/d converter figure 9-2. format of a/d converter mode register ( m pd78018f, 78018fy, 78014h subseries) adm3 adm2 adm1 selects analog input channel 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7 fr1 fr0 hsc selects a/d conversion time note 1 at f x = 10.0 mhz at fx = 8.38 mhz at fx = 5.0 mhz at fx = 4.19 mhz 0 0 1 160/f x setting prohibited note 2 19.1 m s 32.0 m s 38.1 m s 0 1 1 80/f x setting prohibited note 2 setting prohibited note 2 setting prohibited note 2 19.1 m s 1 0 0 100/f x setting prohibited note 2 setting prohibited note 2 20.0 m s 23.9 m s 1 0 1 200/f x 20.0 m s 23.9 m s 40.0 m s 47.7 m s others setting prohibited trg selects external trigger 0 no external trigger (software start) 1 conversion started by external trigger (hardware start) cs controls a/d conversion operation 0 stops operation 1 starts operation notes 1. set the a/d conversion time to 19.1 m s or longer. 2. these settings are prohibited because the a/d conversion time is less than 19.1 m s. cautions 1. to reduce the power consumption of the a/d converter when the standby function is used, stop the a/d conversion operation by clearing bit 7 (cs) to 0, and then execute the halt or stop instruction. 2. to resume the a/d conversion operation which has been once stopped, clear the interrupt request flag (adif) to 0 and then start the a/d conversion operation. remark f x : main system clock oscillation frequency 765432 symbol 10 ff80h hsc adm adm1 adm3 adm2 fr0 fr1 trg cs address at reset r/w 01h r/w
266 chapter 9 applications of a/d converter figure 9-3. format of a/d converter mode register ( m pd780024, 780024y subseries) ega01 ega00 specifies external trigger signal and edge 0 0 no external trigger 0 1 detects falling edge 1 0 detects rising edge 1 1 detects both rising and falling edges fr02 fr01 fr00 selects conversion time note 1 0 0 0 144/f x (17.1 m s) 0 0 1 120/f x (14.3 m s) 0 1 0 96/f x (setting prohibited note 2 ) 1 0 0 72/f x (setting prohibited note 2 ) 1 0 1 60/f x (setting prohibited note 2 ) 1 1 0 48/f x (setting prohibited note 2 ) others setting prohibited trg0 selects software start/hardware start 0 software start 1 hardware start adcs0 controls a/d conversion operation 0 stops operation 1 enables operation notes 1. set the a/d conversion time to 14 m s or longer. 2. these settings are prohibited because the a/d conversion time is less than 14 m s. remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 8.38 mhz 7 adcs0 6 trg0 5 fr02 4 fr01 3 fr00 2 ega01 1 ega00 0 0 symbol adm0 address ff80h at reset 00h r/w r/w
267 chapter 9 applications of a/d converter figure 9-4. format of a/d converter mode register ( m pd780924 subseries) ega01 ega00 specifies external trigger signal and edge 0 0 no external trigger 0 1 detects falling edge 1 0 detects rising edge 1 1 detects both rising and falling edges fr02 fr01 fr00 selects conversion time 0 0 0 144/f x (17.1 m s) 0 0 1 120/f x (14.3 m s) 1 0 0 288/f x (34.4 m s) 1 0 1 240/f x (28.6 m s) 1 1 0 192/f x (22.9 m s) others setting prohibited trg0 selects software start/hardware start 0 software start 1 hardware start adcs0 controls a/d conversion operation 0 stops operation 1 enables operation note set the a/d conversion time to 14 m s or longer remarks 1. f x : main system clock oscillation frequency 2. ( ): f x = 8.38 mhz 7 adcs0 6 trg0 5 fr02 4 fr01 3 fr00 2 ega01 1 ega00 0 0 symbol adm0 address ff80h at reset 00h r/w r/w
268 chapter 9 applications of a/d converter figure 9-5. format of a/d converter input select register ( m pd78014, 78014y, 78018f, 78018fy, 78014h subseries) cautions 1. set analog input channels in the following steps: <1> set the number of analog input channels by using adis. <2> select one channel whose data is to be converted, from the channels selected by adis, by using the a/d converter mode register (adm). 2. the internal pull-up resistor is not used to the channel selected by adis as an analog input channel, regardless of the value of the bit 1 (puo1) of the pull-up resistor option register (puo). 765432 symbol 10 adis3 selects number of analog input channels ff84h adis0 adis adis1 adis3 adis2 0 0 0 0 address at reset r/w 00h r/w adis2 adis1 adis0 0 no analog input channel (p10-p17) 000 0 1 channel (anl0, p11-p17) 001 0 2 channels (anl0, anl1, p12-p17) 010 0 3 channels (anl0-anl2, p13-p17) 011 0 4 channels (anl0-anl3, p14-p17) 100 0 5 channels (anl0-ani4, p15-p17) 101 0 6 channels (anl0-ani5, p16-p17) 110 0 7 channels (ani0-anl6, p17) 111 1 8 channels (ani0-ani7) 000 others setting prohibited
269 chapter 9 applications of a/d converter figure 9-6. format of a/d converter input select register ( m pd780001) cautions 1. set analog input channels in the following steps: <1> set the number of analog input channels by using adis. <2> select one channel whose data is to be converted, from the channels selected by adis, by using the a/d converter mode register (adm). 2. the internal pull-up resistor is not used to the channel selected by adis as an analog input channel, regardless of the value of the bit 1 (puo1) of the pull-up resistor option register (puo). figure 9-7. format of analog input channel specification register ( m pd780024, 780024y, 780924 subseries) ads02 ads01 ads00 specifies analog input channel 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7 765432 symbol 10 adis3 selects number of analog input channels ff84h adis0 adis adis1 adis3 adis2 0 0 0 0 address at reset r/w 08h r/w adis2 adis1 adis0 1 8 channels (ani0-ani7) 000 others setting prohibited 0 0 0 0 0 ads02 ads01 ads00 symbol ads0 address ff81h at reset 00h r/w r/w 765432 10
270 chapter 9 applications of a/d converter 9.1 level meter in this application example, the analog voltage input to the a/d converter is displayed on an led matrix consisting of 4 4, i.e., 16 leds. in the example shown in this section, the m pd78014 subseries is used. because a level meter has been included in this example, the led display is given in decibel units. figure 9-8 shows the circuit of the level meter, and figure 9-9 shows the relations between the result of the a/d conversion and the number of display digits. figure 9-8. example of level meter circuit figure 9-9. a/d conversion result and display 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0ah ?2 12h ?7 20h ?2 2eh ? 39h ? 40h ? 48h ? 51h ? 5bh ? 66h ? 72h ? 80h 0 90h 1 a2h 2 b5h 3 ffh 6 [db] displa y value display level led(units) p60 p61 p62 p63 p64 p65 p66 p67 anin = pd78014 m
271 chapter 9 applications of a/d converter the level meter in this example operates with specifications <1> through <3> below. <1> measurement method a/d conversion is performed every 20 ms, and the average value of four previous data is calculated and displayed on the leds. <2> display method the led display is updated every 20 ms. the led matrix consists of 4 4 = 16 leds and performs dynamic display. for the dynamic display, 8-bit timer/event counter 1 (interval time: 2 ms) is used. <3> peak hold holding the maximum display level for a specific period (1 second) is called peak hold. even if the display level drops during a specific period, only the led at the maximum display level is held. therefore, the hold period of the hold level is 20 ms to 1 s. figure 9-10. concept of peak hold (1) description of package level : name of led display subroutine dsplev : display level storage area hldlev : hold level storage area ct20ms : counter measuring 20 ms ct1s : counter measuring 1 s ax, hl, bc (subroutine processing) bank 0: a, hl, b (interrupt processing) specific period (1 second) hold level 666678999999444566 display level 654578987655433562
272 chapter 9 applications of a/d converter name usage attribute bytes addat stores a/d conversion value saddr 4 dsplev stores display level 1 hldlev stores hold level ct20ms counter measuring 20 ms ct1s counter measuring 1 s digcnt display digit counter dspdat stores display data 4 workct work counter for loop processing 1 name usage t20msf set every 20 ms t1sf set every 1 s 2 levels 5 bytes ? a/d converter ? 8-bit timer/event counter 1 ? p6 ? selects channel of a/d converter and starts operation adm = #1000 1b ? interval time of 2 ms of 8-bit timer/event counter 1 tcl1 = #10111011b tmc1 = #00000001b cr10 = 130 ? p6 output mode ? makes p6 output latch low ? enables inttm1 interrupt
273 chapter 9 applications of a/d converter this program performs two types of processing: a/d conversion (subroutine) and led display (interrupt). ? a/d conversion processing call level at least once every 20 ms from the main processing. the level processing performs a/d conversion processing only when 20 has elapsed. ? led display the 4 4 led matrix performs dynamic display by using the interrupt processing of 8-bit timer/event counter 1 (interval: 2 ms). the interrupt processing of 8-bit timer/event counter 1 sets the t20msf (loading of a/d conversion value) and t1sf (end of hold period) used for the a/d conversion processing at an interval of 2 ms. (2) example of use extrn level,ct20ms,ct1s mov ct20ms,#10 mov ct1s,#50 mov tmc2,#00100110b clr1 tmmk3 p6=#00h pm6=#00000000b adm=#10000001b tcl1=#10111011b cr10=#130 tmc1=#00000001b clr1 tmmk1 ei ; turns off led display ; ani0 pin starts operation ; sets 8-bit timer/event counter 1 to 2 ms ; enables 8-bit timer/event counter 1 interrupt
274 chapter 9 applications of a/d converter (3) spd chart level if: 20 ms elapses (t20msf = 1) then else inttm1 selects register bank 0 clears t20msf stores a/d conversion value to memory averages four previous a/d conversion values (for: workct = #0; workct < #16; workct + +) if: conversion result > display level comparison data updates comparison data break stores display data to memory if: less then 1 second (t1sf = 0) then if: hold level < display level then sets display level to hold level then else clears t1sf sets display level to hold level converts display level and hold level to segment signal stores digit signal and segment signal to memory in combination outputs off signal to digit and segment outputs memory contents indicated by digit counter increments digit counter decrements 20 ms counter if: 20 ms elapses (ct20ms = 0) sets 20 ms counter to 10 sets 20 ms elapse status sets t20msf decrements 1-s counter if: 1 second elapses (ct1s = 0) sets 1-s counter to 50 sets 1-s elapse status sets t1sf then then
275 chapter 9 applications of a/d converter (4) program list public level,hldlev,dsplev,ct20ms,ct1s ad_dat dseg saddr addat: ds 4 dsplev: ds 1 hldlev: ds 1 ct20ms: ds 1 ct1s: ds 1 digcnt: ds 1 dspdat: ds 4 workct: ds 1 ad_flg bseg t20msf dbit t1sf dbit vetm1 cseg at 16h dw inttm1 ad_seg cseg ;********************************* * sets level meter data ;********************************* level: if_bit(t20msf) clr1 t20msf a=adcr a<->addat a<->addat+1 a<->addat+2 a<->addat+3 ax=#0h hl=#addat for(workct=#0;workct<#4;workct++) a+=[hl] hl++ if_bit(cy) x++ endif next a<->x c=#4 ax/=c if(c>=#2) (a) x++ endif hl=#levtbl b=#0 for(workct=#0;workct<#16;workct++) if(x>=[hl+b]) (a) b++ else break endif next ; a/d conversion result storage area ; display level value ; hold level value ; 20 ms counter ; 1 s counter ; display digit counter ; display data ; measures 20 ms ; measures 1 s ; sets vector address of 8-bit timer/event counter 1 ; checks 20 ms ; inputs a/d conversion value ; stores a/d conversion value ; averages four a/d conversion values ; data storage address ; carry ; higher digit ; averages four values ; ax/c = ax (quotient) ... c (remainder) ; remainder processing (2 or higher is carried) ; carry processing ; conversion result storage register ; compares data
276 chapter 9 applications of a/d converter dsplev=b (a) if_bit(!t1sf) x=hldlev (a) if(xx a|=[hl+c] a<->x c++ a|=[hl+c] bc=ax hl=#dspdat a=c a&=#0fh a|=#00010000b [hl]=a hl++ a=c a>>=1 a>>=1 a>>=1 a>>=1 a&=#0fh a|=#00100000b [hl]=a hl++ a=b a&=#0fh a|=#01000000b [hl]=a hl++ a=b a>>=1 a>>=1 a>>=1 a>>=1 a&=#0fh a|=#10000000b [hl]=a endif ; determines display data ; 1 s (hold level updated) ; compares hold and display levels ; creates display level ; creates hold level ; sets segment signal of first digit ; sets digit signal ; sets segment signal of second digit ; sets digit signal ; sets segment signal of third digit ; sets digit signal ; sets segment signal of fourth digit ; sets digit signal
277 chapter 9 applications of a/d converter ret levtbl: db 0ah db 12h db 20h db 2eh db 39h db 40h db 48h db 51h db 5bh db 66h db 72h db 80h db 90h db 0a2h db 0b5h db 0ffh dsptbl: dw 0000000000000000b dw 0000000000000001b dw 0000000000000011b dw 0000000000000111b dw 0000000000001111b dw 0000000000011111b dw 0000000000111111b dw 0000000001111111b dw 0000000011111111b dw 0000000111111111b dw 0000001111111111b dw 0000011111111111b dw 0000111111111111b dw 0001111111111111b dw 0011111111111111b dw 0111111111111111b dw 1111111111111111b hldtbl: dw 0000000000000000b dw 0000000000000001b dw 0000000000000010b dw 0000000000000100b dw 0000000000001000b dw 0000000000010000b dw 0000000000100000b dw 0000000001000000b dw 0000000010000000b dw 0000000100000000b dw 0000001000000000b dw 0000010000000000b dw 0000100000000000b dw 0001000000000000b dw 0010000000000000b dw 0100000000000000b dw 1000000000000000b $eject
278 chapter 9 applications of a/d converter ;********************************* * level meter data ;********************************* tm1_seg cseg inttm1: sel rb0 p6=#00000000b hl=#dspdat b=digcnt (a) p6=[hl+b] (a) digcnt++ digcnt&=#00000011b ct20ms-- if(ct20ms==#0) ct20ms=#10 set1 t20msf ct1s-- if(ct1s==#0) ct1s=#50 set1 t1sf endif endif reti ; turns off digit and segment signals ; 20 ms? ; sets initial counter value ; 1s? ; sets initial counter value
279 chapter 9 applications of a/d converter 9.2 thermometer in this application example, a temperature in a range of C20 c to +50 c is measured by using a thermistor (6 k w / 0 c) as a temperature sensor. changes in the resistance of the thermistor with respect to temperature are given by the following expression: r = r 0 exp { b (1/t C 1/t 0 ) } where, r : resistance at given temperature t [ k] t : given temperature [ k] r 0 : resistance at reference temperature t 0 [ k] t 0 : reference temperature [ k] b : constant obtained by reference temperature t 0 [ k] and t 0 [ k] constant b changes with the temperature. this constant can be calculated by changing the above expression as follows: 1r b = in (1/tC1/t 0 )r 0 figure 9-11 shows a circuit example. this circuit is designed to input 0 v at C20 c, and 5 v at + 50 c. figure 9-11. circuit example of thermometer pd78014 m anin + th
280 chapter 9 applications of a/d converter because the characteristic of the thermistor is non linear in this example, the input analog voltage is not converted to a temperature in a range of C20 c to +50 c through calculation but by comparison with table data. this conversion result is stored to ram (dspdat) as 2-digit bcd. figure 9-12 shows the characteristics of the thermistor, and table 9-1 shows the relations between temperature and a/d conversion value. to measure the temperature, four conversion values are averaged and converted to a temperature. the result of the conversion is stored in a display area. therefore, the data is updated once every four times. for example, if measurement processing is executed every 250 ms, the display updating cycle is 1 second. figure 9-12. temperature vs. output characteristic 100 90 80 70 60 50 40 30 20 10 0 ?0 ?0 0 10 20 30 40 50 temperature (?) percentage of output characteristic (%)
281 chapter 9 applications of a/d converter table 9-1. a/d conversion value and temperature conversion temperature conversion temperature conversion temperature conversion temperature value [ c] value [ c] value [ c] value [ c] 00 C20.0 38 C2.5 82 15.5 cb 33.5 01 C19.5 3c C1.5 86 16.5 ce 34.5 04 C18.5 40 C0.5 8b 17.5 d2 35.5 07 C17.5 44 0.5 8f 18.5 d6 36.5 0a C16.5 48 1.5 93 19.5 d9 37.5 0c C15.5 4c 2.5 97 20.5 dc 38.5 0f C14.5 50 3.5 9b 21.5 e0 39.5 12 C13.5 54 4.5 9f 22.5 e3 40.5 16 C12.5 58 5.5 a3 23.5 e7 41.5 19 C11.5 5c 6.5 a8 24.5 ea 42.5 1c C10.5 60 7.5 ac 25.5 ed 43.5 1f C9.5 64 8.5 b0 26.5 f0 44.5 23 C8.5 69 9.5 b4 27.5 f3 45.5 26 C7.5 6d 10.5 b7 28.5 f6 46.5 2a C6.5 71 11.5 bb 29.5 f9 47.5 2d C5.5 75 12.5 bf 30.5 fc 48.5 31 C4.5 7a 13.5 c3 31.5 fe 49.5 35 C3.5 7e 14.5 c7 32.5 ff 50.0 (1) description of package thmeter : thermometer subroutine call name dspdat : display data storage area cntpro : test counter counting number of inputs minusf : minus temperature display flag t250msf : 250-ms setting flag ax, bc, hl
282 chapter 9 applications of a/d converter name usage attribute bytes addat stores a/d conversion value saddr 4 dspdat stores display data 2 cntpro test counter for number of inputs 1 workct work counter for loop processing name usage t250msf executes measurement processing when set minusf set when temperature is below zero 1 level 2 bytes a/d converter selects a/d converter channel and starts operation adm = #1000 1b; set the t250msf flag in each measurement cycle by using timer processing. after that, call thmeter at least once in measurement cycle.
283 chapter 9 applications of a/d converter (2) example of use extrn thmeter,dspdat,cntpro extbit minusf,t250msf ad_dat dseg saddr ct250ms:ds 1 ledd: ds 4 digct: ds 1 vetm3 cseg at 12h dw inttm3 mov tmc2,#00100110b clr1 tmmk3 ct250ms=#128 cntpr0=#4 adm=#10000011b ;********************************************** ; watch timer interrupt processing ; interval time: 1.95 ms ;********************************************** inttm3: dbnz ct250ms,$rtntm3 mov ct250ms,#128 set1 t250msf rtntm3: reti . . . . . . . . . . . . . . . . ; 250 ms counter ; led display area ; led display digit counter ; sets vector address of watch timer ; sets watch timer to 1.95 ms ; selects ani1 pin and starts operation ; 1.95 ms interrupt processing ; 250 ms elapses
284 chapter 9 applications of a/d converter (3) spd chart thmeter if: 250 ms elapses (t250ms = 1) then else clears t250ms stores a/d conversion value to memory if: four values stored in memory then averages four a/d conversion values (for: workct = #0; workct < #70; workct + +) if: conversion result > comparison data for temperature conversion then updates comparison data break if: minus temperature data then sets minus status sets minusf converts temperature data to decimal number and stores in memory
285 chapter 9 applications of a/d converter (4) program list public thmeter,dspdat,cntpr0,t250msf,minusf ad_dat dseg saddr addat: ds 4 dspdat: ds 2 cntpr0: ds 1 workct: ds 1 ad_flg bseg t250msf dbit minusf dbit th_seg cseg ;********************************* * sets temperature data ;********************************* thmeter: if_bit(t250msf) clr1 t250msf a=adcr a<->addat a<->addat+1 a<->addat+2 a<->addat+3 cntpr0-- if(cntpr0==#0) cntpr0=#4 ax=#0h hl=#addat for(workct=#0;workct<#4;workct++) a+=[hl] hl++ if_bit(cy) x++ endif next a<->x c=#4 ax/=c if(c>=#2) (a) x++ endif a=x b=#0 hl=#thrtbl if(a==#0ffh) b=#70 else for(workct=#0;workct<#70;workct++) if(x>=[hl+b]) (a) b++ else break endif next ; a/d conversion result storage area ; display data ; tests number of inputs ; sets 250 ms ; sets minus data ; 250 ms ; data storage address ; carry occurs ; carry ; ax/c = ax (quotient) ... c (remainder) ; remainder processing (2 digits or more carried) ; carry processing ; converts to temperature data
286 chapter 9 applications of a/d converter endif clr1 minusf a=#20 bC=a if_bit(cy) set1 minusf a=#0 aC=b a<->b endif x=#0 a=b a<->x c=#10 ax/=c dspdat=c (a) (dspdat+1)=x (a) endif endif ret ; temperature data 20 ; to decimal conversion ; absolute value of data ; decimal conversion ; temperature data/10 ; updates display data
287 chapter 9 applications of a/d converter thrtbl; ; db 1 ; C19.5 db 4 ; C18.5 db 7 ; C17.5 db 0ah ; C16.5 db 0ch ; C15.5 db 0fh ; C14.5 db 12h ; C13.5 db 16h ; C12.5 db 19h ; C11.5 db 1ch ; C10.5 db 1fh ; C9.5 db 23h ; C8.5 db 26h ; C7.5 db 2ah ; C6.5 db 2dh ; C5.5 db 31h ; C4.5 db 35h ; C3.5 db 38h ; C2.5 db 3ch ; C1.5 db 40h ; C0.5 db 44h ; +0.5 db 48h ; 1.5 db 4ch ; 2.5 db 50h ; 3.5 db 54h ; 4.5 db 58h ; 5.5 db 5ch ; 6.5 db 60h ; 7.5 db 64h ; 8.5 db 69h ; 9.5 db 6dh ; 10.5 db 71h ; 11.5 db 75h ; 12.5 db 7ah ; 13.5 db 7eh ; 14.5 db 82h ; 15.5 db 86h ; 16.5 db 8bh ; 17.5 db 8fh ; 18.5 db 93h ; 19.5 db 97h ; 20.5 db 9bh ; 21.5 db 9fh ; 22.5 db 0a3h ; 23.5 db 0a8h ; 24.5 db 0ach ; 25.5 db 0b0h ; 26.5 db 0b4h ; 27.5 db 0b7h ; 28.5 db 0bbh ; 29.5 db 0bfh ; 30.5 db 0c3h ; 31.5 db 0c7h ; 32.5 db 0cbh ; 33.5 db 0ceh ; 34.5 db 0d2h ; 35.5 db 0d6h ; 36.5
288 chapter 9 applications of a/d converter db 0d9h ; 37.5 db 0dch ; 38.5 db 0e0h ; 39.5 db 0e3h ; 40.5 db 0e7h ; 41.5 db 0eah ; 42.5 db 0edh ; 43.5 db 0f0h ; 44.5 db 0f3h ; 45.5 db 0f6h ; 46.5 db 0f9h ; 47.5 db 0fch ; 48.5 db 0feh ; 49.5
289 chapter 9 applications of a/d converter 9.3 analog key input in this example, sixteen keys are input by using the a/d converter. to input keys, a circuit must be designed so that a voltage peculiar to a key is input to the a/d converter when the key is pressed. in the example shown in this section, the m pd78014 subseries is used. because sixteen keys are input in this example, v dd is divided by 16 and the voltage of each key is converted into a key code. table 9-2 shows the relations between the input voltages and key codes (00h through 0fh). when no key input is made, the key code is 10h. table 9-2. input voltage and key code input voltage v a/d conversion value key code gnd 00-07h 00h 1/16v dd 08-17h 01h 2/16v dd 18-27h 02h 3/16v dd 28-37h 03h 4/16v dd 38-47h 04h 5/16v dd 48-57h 05h 6/16v dd 58-67h 06h 7/16v dd 68-77h 07h 8/16v dd 78-87h 08h 9/16v dd 88-97h 09h 10/16v dd 98-a7h 0ah 11/16v dd a8-b7h 0bh 12/16v dd b8-c7h 0ch 13/16v dd c8-d7h 0dh 14/16v dd d8-e7h 0eh 15/16v dd e8-f7h 0fh v dd f8-ffh 10h figure 9-13 shows an example of the circuit that satisfies the above relations between the input voltages and key codes. note, however, that this circuit gives a priority to the key with the lower number if two or more keys are pressed at the same time.
290 chapter 9 applications of a/d converter figure 9-13. example of analog key input circuit resistances r0 through r15 used in the circuit in figure 9-13 can be calculated by the following expression: n r0 r k = 16 C n table 9-3 shows the resistances of r1 through r15 where r0 is 1 k w in the above expression (the calculation result of a resistance may slightly different from the resistance of commercial resistors indicated by a color code). table 9-3. resistances of r1 through r5 resistor no. resistance value w resistor no. resistance value w resistor no. resistance value w r1 68 r6 150 r11 560 r2 75 r7 180 r12 750 r3 82 r8 220 r13 1.3 k r4 100 r9 270 r14 2.7 k r5 120 r10 390 r15 8.2 k this program converts an input analog voltage into the corresponding key code shown in table 9-2, absorbs chattering, and then stores the input voltage to ram. to absorb chattering, a key code is assumed to be valid when it coincides with a given value five times in succession. for example, if an analog voltage is sampled every 5 ms, chattering of 20 to 25 ms is absorbed. if a key input is changed, a key change flag (keychg) is set. n s k=1 anin v dd pd78014 m k0 k1 k2 k14 k15 r0 r1 r2 r14 r15
291 chapter 9 applications of a/d converter (1) description of package akeyin : analog key input subroutine name keydat : key code storage area pastdt : key code storage area for chattering absorption chatct : chattering absorption counter keychg : key change test flag chtendf : flag to test end of chattering absorption keyoff : key code when there is no key input a name usage attribute bytes pastdat stores key code for chattering absorption saddr 1 keydat stores key code chatcnt chattering counter name usage keychg set when key is changed chtendf sets when chattering absorption ends 1 level 2 bytes a/d converter selects a/d converter channel and starts operation adm = #1000 1b ? call akeyin at fixed interval. ? input a key code after testing the key change flag. note that this flag is not cleared by the subroutine and must be cleared after the flag has been tested.
292 chapter 9 applications of a/d converter (2) example of use extrn akeyin,keydat,pastdt,chatct extrn keyoff extbit keychg,chtendf vetm3 cseg at 12h dw inttm3 maindat dseg saddr ct5ms: ds 1 tmc2=#00100110b clr1 tmmk3 ct5ms=#3 keydat=#keyoff pastdt=#keyoff chatct=#chaval clr1 chtendf clr1 keychg adm=#10000101b ei if_bit(keychg) clr1 keychg ; key input processing endif ;********************************************** ; watch timer interrupt processing ; interval: 1.95 ms ;********************************************** inttm3: dbnz ct5ms,$rtntm3 mov ct5ms,#3 call !akeyin rtntm3: reti . . . . . . . . . . . . . . . . ; sets vector address of watch timer ; sets off data as key data ; sets number of times of chattering to five ; selects ani2 pin and starts operation ; key changed? ; 1.95 ms interrupt processing ; 1.95 ms 3 elapses
293 chapter 9 applications of a/d converter (3) spd chart akeyin inputs and adjusts a/d conversion value (adds 8) then else if: overflow occurs sets no key input status decodes key if: key input not changed if: chattering being absorbed then then if: chattering absorption ends then sets chattering absorption status sets chtendf if: valid key changed then updates key code sets key change status else updates comparison key code sets keychg sets chattering absorption start status clears chtendf
294 chapter 9 applications of a/d converter (4) program list public akeyin,keydat,pastdt public chatct,keyoff public keychg,chtendf ak_dat dseg saddr keydat: ds 1 pastdt: ds 1 chatct: ds 1 ak_flg bseg keychg dbit chtendf dbit keyoff equ 10h chaval equ 5 ak_seg cseg ;****************************** * analog key input ;****************************** akeyin: a=adcr a+=#8 if_bit(cy) a=#keyoff else a>>=1 a>>=1 a>>=1 a>>=1 a&=0fh endif if(a==pastdt) if_bit(!chtendf) chatct-- if(chatct==#0) set1 chtendf a=pastdt if(a!=keydat) keydat=a set1 keychg endif endif endif endif pastdt=a chatct=#chaval-1 clr1 chtendf endif ret ; key data storage area ; chattering key data ; chattering counter ; key changed ; chattering absorption end status ; off key data ; number of times of chattering absorption ; inputs a/d conversion value ; corrects data ; sets no key input status ; decodes key ; no key change ; chattering being absorbed ; end of chattering absorption ; sets chattering absorption status ; valid key changed ; updates key data ; sets key change status ; updates previous key data ; starts chattering absorption
295 chapter 9 applications of a/d converter 9.4 4-channel input a/d conversion this section describes the method to scan four channels for a/d conversion. the a/d conversion operation is started by the software. the analog voltages input to the selected four channels are converted into digital signals. the result of the a/d conversion of each channel is stored in ram. an interrupt request is generated by using 8-bit timer/event counter 1. the result of the conversion is loaded and channel is converted in the processing of this interrupt request. because 8-bit timer/event counter 1 is set to 10 ms, it is not necessary to measure the wait time of the a/d conversion. caution to change the interrupt time, make the following setting: ? set timer longer than a/d conversion end time + interrupt entry return time + interrupt processing time. ? test flags that indicate the end of the conversion. figure 9-14. timing chart in 4-channel scan mode inttm2 adcr ani0 ani1 ani2 ani3 ani0 ani1 ani2 ani3 ani0 adin 1 23012301 0 10 ms
296 chapter 9 applications of a/d converter (1) description of package ? output parameter m_ch0 : stores conversion result of channel 0 m_ch1 : stores conversion result of channel 1 m_ch2 : stores conversion result of channel 2 m_ch3 : stores conversion result of channel 3 a name usage attribute bytes m_ch0 channel 0 conversion result storage area saddr 1 m_ch1 channel 1 conversion result storage area saddr 1 m_ch2 channel 2 conversion result storage area saddr 1 m_ch3 channel 3 conversion result storage area saddr 1 m_mode mode storage area saddr 1 1 level 3 bytes ? a/d converter ? 8-bit timer/event counter 1 ? port 1 (p10-p13) ? selects a/d converter channel and starts operation adm = #1000 b ? selects number of a/d converter channels adis = #00000100b ? interval time of 8-bit timer/event counter 1: 10 ms tcl1 = #00001110b tmc1 = #00000001b cr10 = #81 ? enables tmmk1 interrupt
297 chapter 9 applications of a/d converter (2) example of use extrn m_ch0,m_ch1,m_ch2,m_ch3,m_mode ;****************************************** ; initialize ;****************************************** m4 cseg ; res_sta: sel rb0 ; di ; adm=#10000001b adis=#00000100b cr10=#81 tcl1=#00001110b tmc1=#00000001b clr1 tmif1 clr1 tmmk1 ei m_mode=#0 while(forever) a=m_ch0 a=m_ch1 a=m_ch2 a=m_ch3 (3) spd chart [a/d conversion processing] . . . . ; starts a/d operation and selects external trigger channel 0 ; selects analog input channel 4 ; sets modulo register 81 ; count clock: 8.2 khz ; enables 8-bit timer/register 1 operation ; clears timer 1 interrupt request flag ; enables timer 1 interrupt ; ; sets initial value (0 channel) to mode area ; ;a ? data of channel 0 ;a ? data of channel 1 ;a ? data of channel 2 ;a ? data of channel 3 . . . . . . . . . . . . kasan loads conversion result of channel for previous a/d conversion changes channel adm ? selects chan g ed channel
298 chapter 9 applications of a/d converter (4) program list ;******************************************** ; a/d conversion ;******************************************** ; $pc(054) ; ; public m_ch0,m_ch1,m_ch2,m_ch3,m_mode ; ; veintm1 cseg at 16h dw kasan ;******************************************** ; ram definition ;******************************************** dseg saddr m_ch0: ds 1 m_ch1: ds 1 m_ch2: ds 1 m_ch3: ds 1 m_mode: ds 1 ; cseg kasan: sel rb2 switch(m_mode) case 0: m_ch0=adcr (a) m_mode++ adm=#10000011b break case 1: m_ch1=adcr (a) m_mode++ adm=#10000101b break case 2: m_ch2=adcr (a) m_mode++ adm=#10000111b break case 3: m_ch3=adcr (a) m_mode=#0 adm=#10000001b break ends reti end ; area for channel 0 addition ; area for channel 1 addition ; area for channel 2 addition ; area for channel 3 addition ; mode storage area ; ; selects bank 2 ; channel currently selected? ; channel 0: ; transfers conversion result to ram ; ; select channel 1: ; ; channel 1: ; transfers conversion result to ram ; ; selects channel 2 ; ; channel 2: ; transfers conversion result to ram ; ; selects channel 3 ; ; channel 3: ; transfers conversion result to ram ; ; selects channel 0 ; ; ;
299 chapter 10 applications of key input chapter 10 applications of key input this chapter introduces an example of a program that inputs signals from a key matrix of 4 8 keys. the key scan be pressed successively, and two or more keys can be pressed simultaneously. in the circuit shown in this section, the high-order 4 bits of port 3 (p34 through p37) are used as key scan signals, and port 4 is used as key return signals. as the pull-up resistor of port 4 for key return, the internal pull-up resistor set by software is used (refer to figure 10-1 ). port 4 of the 78k/0 series has a function to detect the falling edges of the eight port pins in parallel. if port 4 is used for key return signals, therefore, the standby mode can be released through detection of a falling edge, i.e., by key input. in this example, the m pd78014 subseries is used. figure 10-1. key matrix circuit the input keys are stored to ram on a one key-to-1 bit basis. the ram bit corresponding to a pressed key is set and the bit corresponding to a released key is cleared. by testing the ram data on a 1-bit-by-1-bit basis starting from the first bit, the key status can be checked. to absorb chattering, the key is assumed to be valid when four successive key codes coincide with a given code. for example, if a key code is sampled every 5 ms, chattering of 15 ms to 20 ms can be absorbed. if the key input is changed, a key change flag (keychg) is set. p34 p35 p36 p37 p47 = pd78014 m p46 p45 p44 p43 p42 p41 p40 pull-up resistors connected
300 chapter 10 applications of key input (1) description of package keyin : key input subroutine name keydata : key data storage area chatct : chattering counter keychg : key change test flag ax, de, hl name usage attribute bytes keydata stores valid key data saddr 4 work stores key data during chattering chatct chattering counter 1 workct loop processing work counter name usage chgfg set if key input changes keychg set if valid key changes chtend confirms end of chattering 1 level 2 bytes ? p4 ? p3 (p34-p37) ? connects pull-up resistor to p4 puo4 = 1 ? sets high-order 4 bits of p3 in output mode pm3 = #0000 b ? call keyin at specific intervals. ? before inputting the key data, test the key change flag. the key change flag is not cleared by the subroutine. clear the flag after it has been tested.
301 chapter 10 applications of key input (2) example of use extrn akeyin,keydat,pastdt,chatct extrn keyoff extbit keychg,chtendf vetm3 cseg at 12h dw inttm3 maindat dseg saddr ct5ms: ds 1 tmc2=#00100110b clr1 tmmk3 ct5ms=#3 keydat=#keyoff pastdt=#keyoff chatct=#chaval clr1 chtendf clr1 keychg adm=#10000101b ei if_bit(keychg) clr1 keychg ; key input processing endif ;********************************************** ; watch timer interrupt processing ; interval time: 1.95 ms ;********************************************** inttm3: dbnz ct5ms,$rtntm3 mov ct5ms,#3 call !ankeyin rtntm3: reti . . . . . . . . . . . . . . . . . . . . ; sets vector address of watch timer ; sets off data as key data ; sets number of times of chattering to five ; selects ani2 pin and starts operation ; key changed? ; 1.95 ms interrupt ; 1.95 ms 3 elapses
302 chapter 10 applications of key input (3) spd chart keyin outputs key scan signal to p34-p37 then else until: key scan signal output ends key return signal input from p4 if: key input changes sets status in which key input changes chtfg shifts key scan signal 1 bit if: no key input change then if: chattering being absorbed then if: chattering ends then if: valid key changes then sets key change status sets keychg updates key data sets chattering absorption start status clears chtend
303 chapter 10 applications of key input (4) program list public keydata,keychg,keyin,chatct key_dat dseg saddr keydata:ds 4 work: ds 4 chatct: ds 1 workct: ds 1 key_flg bseg chgfg dbit keychg dbit chtend dbit key_seg cseg ;******************************* * matrix key input ;******************************* keyin: clr1 chgfg p3&=#00001111b p3|=#00010000b hl=#work repeat a=p4 a^=#11111111b if(a!=[hl]) set1 chgfg [hl]=a endif hl++ a=p3 a&=#11110000b x=a a=p3 a+=x p3=a until_bit(cy) if_bit(!chgfg) if_bit(!chtend) chatct-- if(chatct==#0) set1 chtend de=#work hl=#keydata for(workct=#0;workct<#4;workct++) if([de]!=[hl]) (a) set1 keychg endif a<->[hl] hl++ de++ next endif endif else chatct=#3 clr1 chtend endif ret ; key data storage area ; chattering key data ; chattering counter ; key change status ; key changed ; chattering absorption end status ; sets address of key work area ; data inverted ; key changed? ; shifts key scan 1 bit ; key changed ; chattering absorbed ; chattering ends ; key changed ; transfers work to keydata
304 chapter 10 applications of key input [memo]
305 appendix a description of spd chart appendix a description of spd chart spd stands for structured programming diagrams. structuring means structuring the logical processing of a program, and designing and formulating the logic by using the basic structure of the logic elements. all programs can be created by only combining the basic structure of logic elements, (sequentially, selectively, or repeatedly). (this is called a structured theorem). through structuring, the flow of a program is clarified, and the reliability is improved. although various methods are available for expressing the structuring of a program, nec employs a diagram technique called spd. the following table describes the spd symbols used for the spd technique and compares them with flowchart symbols. table a-1. comparison between spd symbols and flowchart symbol (1/2) processing name spd symbol flowchart symbol sequential processing conditional branch (if) conditional branch (switch) processing 1 processing 2 processing 1 processing 2 [then] (if: condition) processing 1 processing 2 [else] processing 1 condition then processing 2 else [case: 1] (switch: condition) processing 1 processing 2 [case: 2] processing n [case: n] . . . processing 2 condition processing n processing 1
306 appendix a description of spd chart table a-1. comparison between spd symbols and flowchart symbol (2/2) processing name spd symbol flowchart symbol conditional loop (while) conditional loop (until) conditional loop (for) infinite loop connector (while: condition) processing processing condition then else (until: condition) processing then else processing condition (for: initial value; condition; increment/decrement specification) processing initial value condition processing then increment/ decrement else (while: forever) processing processing [then] (if: condition) goto a a processing condition else then a processing a
307 appendix a description of spd chart 1. sequential processing sequential processing executes processing from top to bottom in the sequence in which processing appears. ? spd chart 2. conditional branch: 2 branch (if) processing contents are selected according to the condition specified by if is true or false (then/else). ? spd chart example 1. identification of positive or negative of x 2. stop if signal is red processing 1 processing 2 (if: condition) processing 1 processing 2 [then] [else] (if: x > 0) x is positive number x is 0 or negative number [then] [else] (if: signal = red) stop [then]
308 appendix a description of spd chart 3. conditional branch: multiple branch (switch) the condition specified by switch is compared with the status indicated by case to select the processing. the processing of the switch statement may be executed only when the given values coincide, or continued downward starting from when the given values coincide (if the processing is not continued downward, break is described). if there is no coincide status, default processing is executed (description of default is arbitrary). (1) execution only on coincidence ? spd chart example displays name of month by input characters (switch: condition) [case: status 1] processing 1 break [case: status 2] processing 2 break [case: status n] processing n [default] processing 0 when status 1: processing 1 when status 2: processing 2 when status n: processing n if status does not coincide: processing 0 . . . . . . . . . . (execution) . . . . . . (switch: input character) [case: '1'] displays jan break [case: '2'] displays feb break [default] displays error . . . . . .
309 appendix a description of spd chart (2) if processing continues from coincidence status ? spd chart example transmission/reception of serial interface 4. conditional loop (while) the condition indicated by while is judged. if the condition is satisfied, processing is repeatedly executed (if the condition is not satisfied from the start, the processing is not executed). ? spd chart example buffers key until return key is input (switch: condition) [case: status 1] processing 1 [case: status 2] processing 2 [case: status n] processing n [default] processing 0 . . . . . . when status 1: processing 1 ? processing 2 ? ... ? processing n when status 2: processing 2 ? ... ? processing n when status n: processing n if status does not coincide: processing 0 (execution) . . . . . . . . . . (switch: transfer mode) [case: 1] address transmission [case: 2] [case: 3] data transmission break data reception when status 1: address transmission ? data transmission when status 2: data transmission when status 3: data reception (execution) (while: condition) processing (while: not return key) inputs 1 character key stores input key to buffer
310 appendix a description of spd chart 5. conditional loop (until) the condition indicated by until is judged after processing has been executed, and the processing is repeatedly executed until a given condition is satisfied (even if the condition is not satisfied from the start, the processing is executed once). ? spd chart example multiplies value of b register by 10 and stores result to a register 6. conditional loop (for) while the condition of the parameter indicated by for is satisfied, processing is repeatedly executed. ? spd chart example clears 256 bytes to 0 starting from address hl (until: condition) processing initializes a register sets value to b register stores 10 to counter (until: counter = 0) a = a + b decrements counter (for: initial value; condition; increment/decrement specification) processing sets first address to hl register (for: workct = #0; workct < #256; workct + +) clears address hl to 0 increments hl register
311 appendix a description of spd chart 7. infinite loop if forever is set as the condition of while, processing is infinitely executed. ? spd chart example to execute main processing repeatedly 8. connector (goto) unconditionally branches to a specified address. ? spd chart (1) to branch to same module (while: forever) processing (while: forever) decodes key stores key code to display area main processing err (if: condition) [then] goto err processing . . .
312 appendix a description of spd chart (2) to branch to different module example to select a parameter at the start address of a subroutine and set wait state 9. connector (continuation) used when the spd of one module requires two or more pages to indicate the flow of processing. ? spd chart (if: condition) [then] sub_er processing goto err (sub_er) ; module name err processing . . . wait10 sets 10 to a register goto wait wait20 sets 20 to a register goto wait wait30 sets 30 to a register wait (until: a = 0) decrements a 1 processing 1 processing 2 1 processing 3 processing 4
313 appendix b revision history appendix b revision history here is the revision history of this document. chapter indicates the location of the preceding edition which has been revised. (1/3) edition major revision from previous edition chapter throughout 5th edition addition of following sections from 78k/0 series application note (basic ii): 2.7 binary multiplication (16 bits 16 bits) 2.8 binary division (32 bits ? 16 bits) 8.5 half-duplex start-stop synchronization communication 9.4 4-channel input a/d conversion deletion of m pd78044, 78054, and 78064 series as applicable models (deleted description is planned to be included in basic ii and iii.) correction of count clock frequency of watchdog timer in format of timer clock select register addition of note on using p30/to0 pin as timer output pin to format of port mode register 3 addition of m pd78002 and 78002y series to format of timer clock select register 3 addition of note on using wake-up function to format of interrupt timing specification register addition of note on deletion of busy mode to format of serial bus interface control register correction of (2) example in 8.1.1 communication in 2-wire serial i/o mode correction of 8.2 interface with osd lsi ( m pd6451a) as follows: (1) description of package deletion of correction of to 1 level 2 bytes deletion of enabling serial interface channel 1 interrupt from deletion of trend from (2) example deletion of trend deletion of enabling serial interface channel 1 interrupt (3) spd chart, (4) program list deletion of setting of transfer completion status correction of program of transfer processing of sbi data in (4) program list in 8.3.1 application as master cpu chapter 4 application of watchdog timer chapter 7 application of watch timer chapter 5 application of 16- bit timer/event counter chapter 8 application of serial interface
314 appendix b revision history throughout chapter 5 application of 16- bit timer/event counter chapter 8 application of serial interface appendix b revision history throughout chapter 4 applications of watchdog timer chapter 5 application of 16-bit timer/event counter chapter 6 applications of 8-bit timer/event counter 6th edition addition of following products as applicable products: m pd78001b(a), 78002b(a) m pd78011b(a), 78012b(a), 78013(a), 78014(a) m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78p018f m pd78011fy, 78012fy, 78013fy, 78014fy, 78015fy, 78016fy, 78p018fy addition of note on rewriting different data to format of timer clock select registers (tcl0, tcl1, tcl2, tcl3) addition of note on selecting mode to clear & start on coincidence between tm0 and cr00 to format of 16-bit timer mode control register description of formats of following registers for each subseries: format of timer clock select register 3 format of serial operation mode register 0 format of serial bus interface control register addition of appendix b revision history addition of following products as applicable products: m pd780024, 780024y, 780034, 780034y, 78014h, 780924, 780964 subseries, m pd78018f, 78018fy, 780001, 78011f(a), 78012f(a), 78013f(a), 78014f(a), 78015f(a), 78016f(a), 78018f(a), 78p018f(a) addition of figure 4-3 format of watchdog timer clock select register addition of note 2 and caution 2 to figure 4-4 format of watchdog timer mode register addition of caution to figure 5-7 format of external interrupt mode register addition of following register formats: figure 5-10 format of prescaler mode register 0 figure 5-11 format of port mode register 7 addition of following register formats: figures 6-2 and 6-3 format of timer clock select register 50 figures 6-4 and 6-5 format of timer clock select register 51 figures 6-6 format of timer clock select register 52 figures 6-8 format of 8-bit timer mode control register 5n figures 6-9 format of 8-bit timer mode control register 50 figures 6-10 format of 8-bit timer mode control register 51 figures 6-11 format of 8-bit timer mode control register 52 figure 6-14 format of port mode register 7 (2/3) edition major revision from previous edition chapter 7th edition
315 appendix b revision history (3/3) edition major revision from previous edition chapter chapter 8 applications of serial interface chapter 9 applications of a/d converter 7th edition addition of table 8-2 registers of serial interface addition of caution to figures 8-6 through 8-8 format of serial operating mode register 0, and note to control of wake-up function addition of caution to figure 8-19 format of automatic transmis- sion/reception interval specification register change of m pd6252 as maintenance part in 8.1 interface with eeprom tm ( m pd6252) addition of (5) and (6) limits when i 2 c bus mode is used to 8.1.2 communication in i 2 c bus mode addition of hsc bit to figure 9-2 format of a/d converter mode register addition of figure 9-7 format of analog input channel specification register
316 appendix b revision history [memo]
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